// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*/
#include <common.h>
cfg);
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+ clrsetbits_le32(&imx_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ cfg);
#else
clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
return 0;
}
+
+int enable_lvds_bridge(u32 lcd_base_addr)
+{
+ u32 reg = 0;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ if (is_cpu_type(MXC_CPU_MX6SX)) {
+ if ((lcd_base_addr != LCDIF1_BASE_ADDR) &&
+ (lcd_base_addr != LCDIF2_BASE_ADDR)) {
+ puts("Wrong LCD interface!\n");
+ return -EINVAL;
+ }
+ } else {
+ debug("This chip not support lvds bridge!\n");
+ return 0;
+ }
+
+ /* Turn on LDB DI0 clocks */
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+
+ /* set LDB DI0 clk select to 011 PLL2 PFD3 200M*/
+ reg = readl(&imx_ccm->cs2cdr);
+ reg &= ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
+ writel(reg, &imx_ccm->cs2cdr);
+
+ reg = readl(&imx_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &imx_ccm->cscmr2);
+
+ /* set LDB DI0 clock for LCDIF PIX clock */
+ reg = readl(&imx_ccm->cscdr2);
+ if (lcd_base_addr == LCDIF1_BASE_ADDR) {
+ reg &= ~MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
+ reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET);
+ } else {
+ reg &= ~MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK;
+ reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET);
+ }
+ writel(reg, &imx_ccm->cscdr2);
+
+ reg = IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[6]);
+
+ reg = readl(&iomux->gpr[5]);
+ if (lcd_base_addr == LCDIF1_BASE_ADDR)
+ reg &= ~0x8; /* MUX LVDS to LCDIF1 */
+ else
+ reg |= 0x8; /* MUX LVDS to LCDIF2 */
+ writel(reg, &iomux->gpr[5]);
+
+ return 0;
+}
+
#endif
#ifdef CONFIG_FSL_QSPI
}
#endif
+
+#if defined(CONFIG_MXC_EPDC)
+#if defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
+void enable_epdc_clock(void)
+{
+ u32 reg = 0;
+
+ /* disable the clock gate first */
+ clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK);
+
+ /* PLL3_PFD2 */
+ reg = readl(&imx_ccm->chsccdr);
+ reg &= ~MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK;
+ reg |= 5 << MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET;
+ writel(reg, &imx_ccm->chsccdr);
+
+ reg = readl(&imx_ccm->chsccdr);
+ reg &= ~MXC_CCM_CHSCCDR_EPDC_PODF_MASK;
+ reg |= 7 << MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET;
+ writel(reg, &imx_ccm->chsccdr);
+
+ reg = readl(&imx_ccm->chsccdr);
+ reg &= ~MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK;
+ reg |= 0 <<MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET;
+ writel(reg, &imx_ccm->chsccdr);
+
+ /* enable the clock gate */
+ setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK);
+}
+#endif
+#endif
+
/***************************************************/
U_BOOT_CMD(
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
-#include <fsl_sec.h>
#include <imx_thermal.h>
#include <mmc.h>
#ifdef CONFIG_IMX_SEC_INIT
#include <fsl_caam.h>
#endif
+#include <hang.h>
+#include <cpu_func.h>
#define has_err007805() \
(is_mx6sl() || is_mx6dl() || is_mx6solo() || is_mx6ull())
}
#endif
+static void init_csu(void)
+{
+#ifdef CONFIG_ARMV7_NONSEC
+ int i;
+ u32 csu = CSU_BASE_ADDR;
+ /*
+ * This is to allow device can be accessed in non-secure world.
+ * All imx6 chips CSU have 40 Config security level registers.
+ */
+ for (i = 0; i < 40; i ++) {
+ *((u32 *)csu + i) = 0xffffffff;
+ }
+#endif
+}
+
static void clear_ldo_ramp(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
#endif
#ifdef CONFIG_MX6SX
-
void pcie_power_up(void)
{
set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */
init_aips();
+ init_csu();
+
/* Need to clear MMDC_CHx_MASK to make warm reset work. */
clear_mmdc_ch_mask();
return 0;
}
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ serialnr->low = fuse->uid_low;
+ serialnr->high = fuse->uid_high;
+}
+#endif
+
#ifndef CONFIG_SPL_BUILD
/*
* cfg_val will be used for
};
#endif
+enum boot_device get_boot_device(void)
+{
+ enum boot_device boot_dev = UNKNOWN_BOOT;
+ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+ uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
+ uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
+ uint bt_dev_port = (soc_sbmr & 0x00001800) >> 11;
+
+ switch (bt_mem_ctl) {
+ case 0x0:
+ if (bt_mem_type)
+ boot_dev = ONE_NAND_BOOT;
+ else
+ boot_dev = WEIM_NOR_BOOT;
+ break;
+ case 0x2:
+ boot_dev = SATA_BOOT;
+ break;
+ case 0x3:
+ if (bt_mem_type)
+ boot_dev = I2C_BOOT;
+ else
+ boot_dev = SPI_NOR_BOOT;
+ break;
+ case 0x4:
+ case 0x5:
+ boot_dev = bt_dev_port + SD1_BOOT;
+ break;
+ case 0x6:
+ case 0x7:
+ boot_dev = bt_dev_port + MMC1_BOOT;
+ break;
+ case 0x8 ... 0xf:
+ boot_dev = NAND_BOOT;
+ break;
+ default:
+ boot_dev = UNKNOWN_BOOT;
+ break;
+ }
+
+ return boot_dev;
+}
+
void set_wdog_reset(struct wdog_regs *wdog)
{
u32 reg = readw(&wdog->wcr);
int arch_misc_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
setup_serial_number();
return 0;
}
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