#define DWL_CLIENT_TYPE_HEVC_DEC 12U
static u32 cfg[HXDEC_MAX_CORES];
+static u32 timeout;
static int hantro_clk_enable(struct device *dev)
{
for (i = HANTRO_DEC_EXT_FIRST_REG; i <= HANTRO_DEC_EXT_LAST_REG; i++)
dec_regs[id][i] = ioread32(dev->hwregs[id] + i*4);
#endif
+
+ if (timeout) {
+ /* Enable TIMEOUT bits in Reg[1] */
+ dec_regs[id][1] = 0x40100;
+ /* Reset HW */
+ ResetAsic(dev);
+ timeout = 0;
+ }
+
/* put registers to user space*/
/* put original registers to user space*/
ret = copy_to_user(Core->regs, dec_regs[id], HANTRO_DEC_ORG_REGS*4);
for (i = 0; i <= HANTRO_G2_DEC_LAST_REG; i++)
dec_regs[id][i] = ioread32(dev->hwregs[id] + i*4);
+ if (timeout) {
+ /* Enable TIMEOUT bits in Reg[1] */
+ dec_regs[id][1] = 0x40100;
+ /* Reset HW */
+ ResetAsic(dev);
+ timeout = 0;
+ }
+
/* put registers to user space*/
ret = copy_to_user(Core->regs, dec_regs[id], HANTRO_G2_DEC_REGS*4);
if (ret) {
long WaitDecReadyAndRefreshRegs(hantrodec_t *dev, struct core_desc *Core)
{
u32 id = Core->id;
+ long ret;
PDEBUG("wait_event_interruptible DEC[%d]\n", id);
- if (wait_event_interruptible(dec_wait_queue, CheckDecIrq(dev, id))) {
+ ret = wait_event_interruptible_timeout(dec_wait_queue, CheckDecIrq(dev, id), msecs_to_jiffies(200));
+ if (ret == -ERESTARTSYS) {
pr_err("DEC[%d] failed to wait_event_interruptible interrupted\n", id);
return -ERESTARTSYS;
+ } else if (ret == 0) {
+ pr_err("DEC[%d] wait_event_interruptible timeout\n", id);
+ timeout = 1;
}
atomic_inc(&irq_tx);
err = PTR_ERR(temp_class);
goto err_out_class;
}
-
+ timeout = 0;
goto out;
err_out_class: