MLK-16188-3 mmc: fsl_esdhc: support tuning for hs200 and sdr104

Support tuning for HS200 and SDR104. Now only 8QM/QXP are supported.
Some code is imported/modified from kernel sdhci-esdhc-imx.c.

On i.MX8QM LPDDR4 ARM2 board, emmc hs200:
Read speed: ~87MB/s
Write speed: ~67MB/s

Original data, emmc hs:
Read speed: ~43MB/s
Write speed: ~40.5MB/s

On i.MX8QM LPDDR4 ARM2 board, SDR104:
Read speed: ~44MB/s
Write speed: ~9.4MB/s

Original data, SD HS:
Read speed: ~22MB/s
Write speed: ~8.5MB/s

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 12ac29e..87e8845 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -26,6 +26,7 @@
 #include <asm-generic/gpio.h>
 #include <power/regulator.h>
 #include <asm/arch/sys_proto.h>
+#include <dm/pinctrl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -36,6 +37,19 @@ DECLARE_GLOBAL_DATA_PTR;
                                IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
                                IRQSTATEN_DINT)
 
+/* Imported/Modified from Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
+#define        ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
+#define        ESDHC_FLAG_ENGCM07207           BIT(2)
+#define        ESDHC_FLAG_USDHC                BIT(3)
+#define        ESDHC_FLAG_MAN_TUNING           BIT(4)
+#define        ESDHC_FLAG_STD_TUNING           BIT(5)
+#define        ESDHC_FLAG_HAVE_CAP1            BIT(6)
+#define        ESDHC_FLAG_ERR004536            BIT(7)
+#define        ESDHC_FLAG_HS200                BIT(8)
+#define        ESDHC_FLAG_HS400                BIT(9)
+#define        ESDHC_FLAG_ERR010450            BIT(10)
+#define        ESDHC_FLAG_HS400_ES             BIT(11)
+
 struct fsl_esdhc {
        uint    dsaddr;         /* SDMA system address register */
        uint    blkattr;        /* Block attributes register */
@@ -68,7 +82,8 @@ struct fsl_esdhc {
        uint    vendorspec;
        uint    mmcboot;
        uint    vendorspec2;
-       char    reserved4[48];
+       uint    tuning_ctrl;    /* on i.MX6/7/8 */
+       char    reserved4[44];
        uint    hostver;        /* Host controller version register */
        char    reserved5[4];   /* reserved */
        uint    dmaerraddr;     /* DMA error address register */
@@ -84,6 +99,19 @@ struct fsl_esdhc {
        uint    scr;            /* eSDHC control register */
 };
 
+struct esdhc_soc_data {
+       u32 flags;
+       u32 caps;
+};
+
+static struct esdhc_soc_data usdhc_imx8qm_data = {
+       .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+                       | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+                       | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
+       .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz
+               | MMC_MODE_HS_52MHz | MMC_MODE_HS,
+};
+
 /**
  * struct fsl_esdhc_priv
  *
@@ -102,13 +130,26 @@ struct fsl_esdhc {
 struct fsl_esdhc_priv {
        struct fsl_esdhc *esdhc_regs;
        unsigned int sdhc_clk;
+       unsigned int clock;
+       unsigned int mode;
        unsigned int bus_width;
+       unsigned int flags;
+       unsigned int caps;
        struct mmc_config cfg;
        struct mmc *mmc;
        struct udevice *dev;
        int non_removable;
        int wp_enable;
        int vs18_enable;
+       int is_ddr;
+       u32 tuning_step;
+       u32 tuning_start_tap;
+       u32 delay_line;
+       uint signal_voltage;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+       struct udevice *vqmmc_dev;
+       struct udevice *vmmc_dev;
+#endif
 #ifdef CONFIG_DM_GPIO
        struct gpio_desc cd_gpio;
        struct gpio_desc wp_gpio;
@@ -368,6 +409,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
        int     err = 0;
        uint    xfertyp;
        uint    irqstat;
+       uint    flags;
        struct fsl_esdhc_priv *priv = mmc->priv;
        struct fsl_esdhc *regs = priv->esdhc_regs;
 
@@ -422,8 +464,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
        esdhc_write32(&regs->xfertyp, xfertyp);
 #endif
 
+       if ((cmd->cmdidx == MMC_SEND_TUNING_BLOCK) ||
+           (cmd->cmdidx == MMC_SEND_TUNING_BLOCK_HS200)) {
+               flags = IRQSTAT_BRR;
+       } else {
+               flags = IRQSTAT_CC | IRQSTAT_CTOE;
+       }
+
        /* Wait for the command to complete */
-       while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
+       while (!(esdhc_read32(&regs->irqstat) & flags))
                ;
 
        irqstat = esdhc_read32(&regs->irqstat);
@@ -485,6 +534,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
                esdhc_pio_read_write(mmc, data);
 #else
+               flags = DATA_COMPLETE;
+               if ((cmd->cmdidx == MMC_SEND_TUNING_BLOCK) ||
+                   (cmd->cmdidx == MMC_SEND_TUNING_BLOCK_HS200)) {
+                       flags = IRQSTAT_BRR;
+               }
+
                do {
                        irqstat = esdhc_read32(&regs->irqstat);
 
@@ -497,7 +552,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
                                err = -ECOMM;
                                goto out;
                        }
-               } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
+               } while (((irqstat & flags) != flags));
 
                /*
                 * Need invalidate the dcache here again to avoid any
@@ -578,6 +633,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
        esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
 #endif
 
+       priv->clock = clock;
 }
 
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
@@ -610,10 +666,221 @@ static void esdhc_clock_control(struct mmc *mmc, bool enable)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(DM_MMC)
+static int esdhc_change_pinstate(struct mmc *mmc)
+{
+       struct udevice *dev = mmc->dev;
+       struct fsl_esdhc_priv *priv = mmc->priv;
+       int ret;
+
+       switch(priv->mode) {
+       case UHS_SDR50:
+       case UHS_DDR50:
+               ret = pinctrl_select_state(dev, "state_100mhz");
+               break;
+       case UHS_SDR104:
+       case MMC_HS_200:
+               ret = pinctrl_select_state(dev, "state_200mhz");
+               break;
+       default:
+               ret = pinctrl_select_state(dev, "default");
+               break;
+       }
+
+       if (ret) {
+               printf("%s %d error\n", __func__, priv->mode);
+       }
+
+       return ret;
+}
+
+static void esdhc_reset_tuning(struct mmc *mmc)
+{
+       struct fsl_esdhc_priv *priv = mmc->priv;
+       struct fsl_esdhc *regs = priv->esdhc_regs;
+
+       if (priv->flags & ESDHC_FLAG_USDHC) {
+               if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+                       esdhc_clrbits32(&regs->autoc12err,
+                                       MIX_CTRL_SMPCLK_SEL |
+                                       MIX_CTRL_EXE_TUNE);
+               }
+       }
+}
+
+static int esdhc_set_timing(struct mmc *mmc)
+{
+       struct fsl_esdhc_priv *priv = mmc->priv;
+       struct fsl_esdhc *regs = priv->esdhc_regs;
+       uint32_t m;
+
+       m = readl(&regs->mixctrl);
+       m &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
+       priv->is_ddr = 0;
+
+       switch (mmc->selected_mode) {
+       case MMC_LEGACY:
+       case SD_LEGACY:
+               esdhc_reset_tuning(mmc);
+               break;
+       case MMC_HS:
+       case MMC_HS_52:
+       case MMC_HS_200:
+       case SD_HS:
+       case UHS_SDR12:
+       case UHS_SDR25:
+       case UHS_SDR50:
+       case UHS_SDR104:
+               writel(m, &regs->mixctrl);
+               break;
+       case UHS_DDR50:
+       case MMC_DDR_52:
+               m |= MIX_CTRL_DDREN;
+               writel(m, &regs->mixctrl);
+               priv->is_ddr = 1;
+               break;
+       default:
+               printf("Not supported %d\n", mmc->selected_mode);
+               break;
+       }
+
+       priv->mode = mmc->selected_mode;
+
+       return esdhc_change_pinstate(mmc);
+}
+
+static int esdhc_set_voltage(struct mmc *mmc)
+{
+       struct fsl_esdhc_priv *priv = mmc->priv;
+       struct fsl_esdhc *regs = priv->esdhc_regs;
+       int ret;
+
+       priv->signal_voltage = mmc->signal_voltage;
+       switch (mmc->signal_voltage) {
+       case MMC_SIGNAL_VOLTAGE_330:
+               if (priv->vs18_enable)
+                       return -EIO;
+               if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
+                       ret = regulator_set_value(priv->vqmmc_dev, 3300000);
+                       if (ret) {
+                               printf("Setting to 3.3V error");
+                               return -EIO;
+                       }
+                       /* Wait for 5ms */
+                       mdelay(5);
+               }
+               esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+               if (!(esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT))
+                       return 0;
+
+               return -EAGAIN;
+       case MMC_SIGNAL_VOLTAGE_180:
+               if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
+                       ret = regulator_set_value(priv->vqmmc_dev, 1800000);
+                       if (ret) {
+                               printf("Setting to 1.8V error");
+                               return -EIO;
+                       }
+               }
+               esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+               if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
+                       return 0;
+
+               return -EAGAIN;
+       case MMC_SIGNAL_VOLTAGE_120:
+               return -ENOTSUPP;
+       default:
+               return 0;
+       }
+}
+
+static int esdhc_execute_tuning(struct mmc *mmc, uint32_t opcode)
+{
+       struct fsl_esdhc_priv *priv = mmc->priv;
+       struct fsl_esdhc *regs = priv->esdhc_regs;
+       u32 irqstaten = readl(&regs->irqstaten);
+       u32 irqsigen = readl(&regs->irqsigen);
+       int i, ret = -ETIMEDOUT;
+       u32 v, m;
+
+       /* clock tuning is not needed for upto 52MHz */
+       if (mmc->clock <= 52000000)
+               return 0;
+
+       /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
+       if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+               v = readl(&regs->autoc12err);
+               m = readl(&regs->mixctrl);
+               v &= ~MIX_CTRL_SMPCLK_SEL;
+               m &= ~MIX_CTRL_FBCLK_SEL;
+               m &= ~MIX_CTRL_AUTO_TUNE_EN;
+
+               v |= MIX_CTRL_EXE_TUNE;
+               m |= MIX_CTRL_FBCLK_SEL;
+               m |= MIX_CTRL_AUTO_TUNE_EN;
+
+               writel(v, &regs->autoc12err);
+               writel(m, &regs->mixctrl);
+       }
+
+       /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
+       v = readl(&regs->mixctrl);
+       v = MIX_CTRL_DTDSEL_READ | (v & ~MIX_CTRL_SDHCI_MASK);
+       writel(v, &regs->mixctrl);
+
+       writel(IRQSTATEN_BRR, &regs->irqstaten);
+       writel(IRQSTATEN_BRR, &regs->irqsigen);
+
+       for (i = 0; i < 40; i++) {
+               u32 ctrl;
+
+               if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
+                       if (mmc->bus_width == 8)
+                               writel(0x7080, &regs->blkattr);
+                       else if (mmc->bus_width == 4)
+                               writel(0x7040, &regs->blkattr);
+               } else {
+                               writel(0x7040, &regs->blkattr);
+               }
+
+               /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
+               v = readl(&regs->mixctrl);
+               v = MIX_CTRL_DTDSEL_READ | (v & ~MIX_CTRL_SDHCI_MASK);
+               writel(v, &regs->mixctrl);
+
+               /* We are using STD tuning, no need to check return value */
+               mmc_send_tuning(mmc, opcode, NULL);
+
+               ctrl = readl(&regs->autoc12err);
+               if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
+                   (ctrl & MIX_CTRL_SMPCLK_SEL)) {
+                       ret = 0;
+                       break;
+               }
+
+               /* Add 2ms delay for SD and eMMC */
+               mdelay(2);
+       }
+
+       writel(irqstaten, &regs->irqstaten);
+       writel(irqsigen, &regs->irqsigen);
+
+       return ret;
+}
+
+static int esdhc_set_vdd(struct mmc *mmc, bool enable)
+{
+       struct fsl_esdhc_priv *priv = mmc->priv;
+
+       return regulator_set_enable(priv->vmmc_dev, enable);
+}
+#endif
+
 static int esdhc_set_ios(struct mmc *mmc)
 {
        struct fsl_esdhc_priv *priv = mmc->priv;
        struct fsl_esdhc *regs = priv->esdhc_regs;
+       int ret;
 
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
        /* Select to use peripheral clock */
@@ -622,7 +889,40 @@ static int esdhc_set_ios(struct mmc *mmc)
        esdhc_clock_control(mmc, true);
 #endif
        /* Set the clock speed */
-       set_sysctl(mmc, mmc->clock);
+       if (priv->clock != mmc->clock)
+               set_sysctl(mmc, mmc->clock);
+
+       if (mmc->clk_disable) {
+#ifdef CONFIG_FSL_USDHC
+       esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
+#else
+       esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
+#endif
+       } else {
+#ifdef CONFIG_FSL_USDHC
+       esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
+#else
+       esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
+       }
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+       if (priv->mode != mmc->selected_mode) {
+               ret = esdhc_set_timing(mmc);
+               if (ret) {
+                       printf("esdhc_set_timing error %d\n", ret);
+                       return ret;
+               }
+       }
+
+       if (priv->signal_voltage != mmc->signal_voltage) {
+               ret = esdhc_set_voltage(mmc);
+               if (ret) {
+                       printf("esdhc_set_voltage error %d\n", ret);
+                       return ret;
+               }
+       }
+#endif
 
        /* Set the bus width */
        esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
@@ -736,6 +1036,12 @@ static const struct mmc_ops esdhc_ops = {
        .set_ios        = esdhc_set_ios,
        .init           = esdhc_init,
        .getcd          = esdhc_getcd,
+#if CONFIG_IS_ENABLED(DM_MMC)
+       .execute_tuning = esdhc_execute_tuning,
+#endif
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+       .set_vdd = esdhc_set_vdd,
+#endif
 };
 
 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
@@ -758,6 +1064,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
        struct fsl_esdhc *regs;
        struct mmc *mmc;
        u32 caps, voltage_caps;
+       u32 val;
 
        if (!priv)
                return -EINVAL;
@@ -770,6 +1077,10 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
 #ifndef CONFIG_FSL_USDHC
        esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
                                | SYSCTL_IPGEN | SYSCTL_CKEN);
+       /* Clearing tuning bits in case ROM has set it already */
+       esdhc_write32(&regs->mixctrl, 0);
+       esdhc_write32(&regs->autoc12err, 0);
+       esdhc_write32(&regs->clktunectrlstatus, 0);
 #else
        esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
                        VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
@@ -837,11 +1148,27 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
                priv->cfg.host_caps &= ~MMC_MODE_8BIT;
 #endif
 
+       priv->cfg.host_caps |= priv->caps;
+
        priv->cfg.f_min = 400000;
-       priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
+       priv->cfg.f_max = min(priv->sdhc_clk, (u32)200000000);
 
        priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
+       writel(0, &regs->dllctrl);
+       if (priv->flags & ESDHC_FLAG_USDHC) {
+               if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+                       val = readl(&regs->tuning_ctrl);
+                       val |= ESDHC_STD_TUNING_EN;
+                       val |= ESDHC_TUNING_START_TAP_DEFAULT;
+                       val &= ~ESDHC_TUNING_START_TAP_MASK;
+                       val |= priv->tuning_start_tap;
+                       val &= ~ESDHC_TUNING_STEP_MASK;
+                       val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
+                       writel(val, &regs->tuning_ctrl);
+               }
+       }
+
        mmc = mmc_create(&priv->cfg, priv);
        if (mmc == NULL)
                return -1;
@@ -985,6 +1312,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
        struct fsl_esdhc_priv *priv = dev_get_priv(dev);
        const void *fdt = gd->fdt_blob;
        int node = dev_of_offset(dev);
+       struct esdhc_soc_data *data = (struct esdhc_soc_data *)dev_get_driver_data(dev);
        fdt_addr_t addr;
        unsigned int val;
        int ret;
@@ -1005,6 +1333,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
 
        priv->esdhc_regs = (struct fsl_esdhc *)addr;
        priv->dev = dev;
+       priv->mode = -1;
+       if (data) {
+               priv->flags = data->flags;
+               priv->caps = data->caps;
+       }
 
        val = fdtdec_get_int(fdt, node, "bus-width", -1);
        if (val == 8)
@@ -1014,6 +1347,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
        else
                priv->bus_width = 1;
 
+       val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
+       priv->tuning_step = val;
+       val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap", 0);
+       priv->tuning_step = val;
+
        if (fdt_get_property(fdt, node, "non-removable", NULL)) {
                priv->non_removable = 1;
         } else {
@@ -1037,15 +1375,24 @@ static int fsl_esdhc_probe(struct udevice *dev)
        priv->vs18_enable = 0;
 
 #ifdef CONFIG_DM_REGULATOR
+       priv->vqmmc_dev = NULL;
+       priv->vmmc_dev = NULL;
        ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
        if (ret) {
                dev_dbg(dev, "no vqmmc supply\n");
        } else {
+               priv->vqmmc_dev = vqmmc_dev;
                if (regulator_get_value(vqmmc_dev) == 1800000)
                        priv->vs18_enable = 1;
        }
+       ret = device_get_supply_regulator(dev, "vmmc-supply", &priv->vmmc_dev);
+       if (ret)
+               dev_dbg(dev, "no vmmc supply\n");
 #endif
 
+       if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
+               priv->caps &= ~UHS_CAPS;
+
        /*
         * TODO:
         * Because lack of clk driver, if SDHC clk is not enabled,
@@ -1093,6 +1440,7 @@ static const struct udevice_id fsl_esdhc_ids[] = {
        { .compatible = "fsl,imx6q-usdhc", },
        { .compatible = "fsl,imx7d-usdhc", },
        { .compatible = "fsl,imx7ulp-usdhc", },
+       { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
        { .compatible = "fsl,esdhc", },
        { /* sentinel */ }
 };

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index ec3e3ad..285f2e0 100644 (file)
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -41,6 +41,27 @@
 #define VENDORSPEC_IPGEN       0x00000800
 #define VENDORSPEC_INIT                0x20007809
 
+#define        MIX_CTRL_DDREN          (1 << 3)
+#define MIX_CTRL_DTDSEL_READ   (1 << 4)
+#define        MIX_CTRL_AC23EN         (1 << 7)
+#define        MIX_CTRL_EXE_TUNE       (1 << 22)
+#define        MIX_CTRL_SMPCLK_SEL     (1 << 23)
+#define        MIX_CTRL_AUTO_TUNE_EN   (1 << 24)
+#define        MIX_CTRL_FBCLK_SEL      (1 << 25)
+#define        MIX_CTRL_HS400_EN       (1 << 26)
+#define        MIX_CTRL_HS400_ES       (1 << 27)
+/* Bits 3 and 6 are not SDHCI standard definitions */
+#define        MIX_CTRL_SDHCI_MASK     0xb7
+/* Tuning bits */
+#define        MIX_CTRL_TUNING_MASK    0x03c00000
+
+#define ESDHC_STD_TUNING_EN             (1 << 24)
+/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
+#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
+#define ESDHC_TUNING_START_TAP_MASK    0xff
+#define ESDHC_TUNING_STEP_MASK         0x00070000
+#define ESDHC_TUNING_STEP_SHIFT                16
+
 #define IRQSTAT                        0x0002e030
 #define IRQSTAT_DMAE           (0x10000000)
 #define IRQSTAT_AC12E          (0x01000000)