MLK-22395 arm64: dts: imx8dxl-phantom-mek: correct the enet pin group

ENET1 pad ring register for compensation cell and voltage reference
is controlled by pin:
	SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD

- move the pin to enet pin group
- format the pin define as alignment
- move out below two pins to hoggrp
	SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD
	SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dxl-phantom-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dxl-phantom-mek.dtsi
index 6d5dea3..2b57f8d 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8dxl-phantom-mek.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8dxl-phantom-mek.dtsi
@@ -220,8 +220,9 @@
 
                pinctrl_hog: hoggrp {
                        fsl,pins = <
-                               SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0       0x0600004c
-                               SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD  0x000514a0
+                               SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0               0x0600004c
+                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD      0x000014a0
+                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD      0x000014a0
                        >;
                };
 
@@ -265,18 +266,17 @@
 
                pinctrl_fec2: fec2grp {
                        fsl,pins = <
-                               SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09  0x06000021
-                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD      0x000014a0
-                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD      0x000014a0
-                               SC_P_ENET0_MDC_CONN_ENET1_MDC                           0x06000020
-                               SC_P_ENET0_MDIO_CONN_ENET1_MDIO                         0x06000020
+                               SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD          0x000514a0
+                               SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09      0x06000021
+                               SC_P_ENET0_MDC_CONN_ENET1_MDC                   0x06000020
+                               SC_P_ENET0_MDIO_CONN_ENET1_MDIO                 0x06000020
                                SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x00000060
-                               SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC                     0x00000060
+                               SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC             0x00000060
                                SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x00000060
                                SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x00000060
                                SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2            0x00000060
                                SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3           0x00000060
-                               SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC                     0x00000060
+                               SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC             0x00000060
                                SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x00000060
                                SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x00000060
                                SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x00000060