MLK-15110-6 arm64: dtsi: fsl-imx8qm: Add DPR0/1/2/3 irq resources for DPU0/1

The Display Prefetch Resolve(DPR) engine is the prefetch engine of DPU.
This patch adds the DPR0/1/2/3's irq resources for DPU0/1.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index 137b27d..259f754 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -1185,7 +1185,9 @@
                             <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+                            <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "irq_common",
                                  "irq_stream0a",
                                  "irq_stream0b",       /* to M4? */
@@ -1193,7 +1195,9 @@
                                  "irq_stream1b",       /* to M4? */
                                  "irq_reserved0",
                                  "irq_reserved1",
-                                 "irq_blit";
+                                 "irq_blit",
+                                 "irq_dpr0",
+                                 "irq_dpr1";
                clocks = <&clk IMX8QM_DC0_PLL0_CLK>,
                         <&clk IMX8QM_DC0_PLL1_CLK>,
                         <&clk IMX8QM_DC0_DISP0_CLK>,
@@ -1473,7 +1477,9 @@
                             <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+                            <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "irq_common",
                                  "irq_stream0a",
                                  "irq_stream0b",       /* to M4? */
@@ -1481,7 +1487,9 @@
                                  "irq_stream1b",       /* to M4? */
                                  "irq_reserved0",
                                  "irq_reserved1",
-                                 "irq_blit";
+                                 "irq_blit",
+                                 "irq_dpr0",
+                                 "irq_dpr1";
                clocks = <&clk IMX8QM_DC1_PLL0_CLK>,
                         <&clk IMX8QM_DC1_PLL1_CLK>,
                         <&clk IMX8QM_DC1_DISP0_CLK>,