arm64: dts: freescale: Add i.MX8QXP 17x17 validation board support

Add i.MX8QXP 17x17 Validation board DT support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index b296003..82323ed 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -65,6 +65,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640
                          imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb imx8qxp-mek-sof.dtb \
                          imx8qxp-mek-rpmsg.dtb imx8qxp-mek-a0.dtb imx8qxp-lpddr4-val-a0.dtb \
                          imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \
-                         imx8qxp-lpddr4-val-spdif.dtb imx8dxp-lpddr4-val.dtb
+                         imx8qxp-lpddr4-val-spdif.dtb imx8dxp-lpddr4-val.dtb imx8qxp-17x17-val.dtb
 
 dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts
new file mode 100644 (file)
index 0000000..4587edd
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qxp.dtsi"
+#include "imx8x-17x17-val.dtsi"
+
+/ {
+    model = "Freescale i.MX8QXP 17x17 Validation Board";
+    compatible = "fsl,imx8qxp-17x17-val", "fsl,imx8qxp";
+};
+

diff --git a/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi b/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi
new file mode 100644 (file)
index 0000000..7a609d2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include "imx8x-val.dtsi"
+
+/ {
+       reserved-memory {
+               linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0 0x14000000>;
+                       alloc-ranges = <0 0x96000000 0 0x14000000>;
+                       linux,cma-default;
+               };
+       };
+
+       regulators {
+               epdev_on: fixedregulator@100 {
+                       compatible = "regulator-fixed";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-name = "epdev_on";
+                       gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+       };
+};
+
+&iomuxc {
+       imx8qxp-lpddr4-arm2 {
+               pinctrl_flexspi0: flexspi0grp {
+                       fsl,pins = <
+                               IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0  0x06000021
+                               IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1  0x06000021
+                               IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2  0x06000021
+                               IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3  0x06000021
+                               IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B  0x06000021
+                               IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK    0x06000021
+                       >;
+               };
+       };
+};
+
+&i2c1 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpi2c1>;
+       status = "okay";
+
+       /delete-node/ gpio@68;
+       /delete-node/ typec@3d;
+
+       pca9557_a: gpio@18 {
+               compatible = "nxp,pca9557";
+               reg = <0x18>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       pca9557_b: gpio@19 {
+               compatible = "nxp,pca9557";
+               reg = <0x19>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+};
+
+&i2c2 {
+       status = "disabled";
+};
+
+&i2c3 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpi2c3>;
+       status = "okay";
+
+       /delete-node/ gpio@18;
+       /delete-node/ gpio@19;
+
+       max7322: gpio@68 {
+               compatible = "maxim,max7322";
+               reg = <0x68>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+};
+
+&i2c_mipi_csi0 {
+       status = "disabled";
+};
+
+&mipi_csi_0 {
+       status = "disabled";
+};
+
+&gpio0_mipi_csi0 {
+       status = "disabled";
+};
+
+&pcieb{
+       ext_osc = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcieb>;
+       clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
+       disable-gpio = <&pca9557_a 5 GPIO_ACTIVE_LOW>;
+       reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+       epdev_on-supply = <&epdev_on>;
+       status = "okay";
+};
+
+&usdhc2 {
+       status = "disabled";
+};
+
+&flexspi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi0>;
+       status = "okay";
+
+       /delete-node/ mt35xu512aba@0;
+
+       flash0: mt25qu512abb@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "micron,mt25qu512abb";
+               spi-max-frequency = <29000000>;
+       };
+};
+
+&adc0 {
+       status = "disabled";
+};
+
+&usbotg1 {
+       /delete-property/ pinctrl-names;
+       /delete-property/ pinctrl-0;
+};