MGS-2842 ARM: imx: correct PFD setting rate flow

According to design, PFD needs to be gated before
setting rate, this patch adds warning for PFD when
there is any try to set PFD rate with gate open;

Since PFD may be enabled during kernel boot up,
here doing enable and disable before setting APLL_PFD2
rate is to make sure it is gated by clock framework
before setting rate.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit bc731e14dc8401efa55fee65948c3ec31c9e5483)

diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index ab1403a..0de0b16 100644 (file)
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -183,7 +183,11 @@ static void __init imx7ulp_clocks_init(struct device_node *scg_node)
                imx_clk_prepare_enable(clks[clks_init_on[i]]);
         imx_clk_set_parent(clks[IMX7ULP_CLK_GPU2D], clks[IMX7ULP_CLK_APLL_PFD2]);
         imx_clk_set_parent(clks[IMX7ULP_CLK_GPU3D], clks[IMX7ULP_CLK_APLL_PFD2]);
-        imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD2], 350000000);
+
+       /* make sure PFD is gated before setting its rate */
+       clk_prepare_enable(clks[IMX7ULP_CLK_APLL_PFD2]);
+       clk_disable_unprepare(clks[IMX7ULP_CLK_APLL_PFD2]);
+       imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD2], 350000000);
 
        pr_info("i.MX7ULP clock tree init done.\n");
 }

diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
index ba0d409..b74f080 100644 (file)
--- a/drivers/clk/imx/clk-pfdv2.c
+++ b/drivers/clk/imx/clk-pfdv2.c
@@ -103,6 +103,10 @@ static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
        u32 val;
        u8 frac;
 
+       /* PFD can NOT change rate without gating */
+       WARN_ON(!(readl_relaxed(pfd->reg) &
+               (1 << ((pfd->idx + 1) * 8 - 1))));
+
        tmp = tmp * 18 + rate / 2;
        do_div(tmp, rate);
        frac = tmp;