MLK-13188-2 dts: imx6ull: change the usdhc root clock to 396MHz
authorHaibo Chen <haibo.chen@nxp.com>
Tue, 6 Sep 2016 05:19:37 +0000 (13:19 +0800)
committerNitin Garg <nitin.garg@nxp.com>
Mon, 19 Mar 2018 19:52:15 +0000 (14:52 -0500)
Due to the errata ERR010450 limit, this patch change the imx6ull
usdhc root clock to 132MHz in soc related dts file, remove all
the root clock setting in board dts file, after this patch,
SDR104/HS200 work at 132MHz, DDR50/DDR52 work at 33MHz.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts
arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts
arch/arm/boot/dts/imx6ull.dtsi

index 69323b6..934e6f6 100644 (file)
@@ -12,9 +12,6 @@
        pinctrl-0 = <&pinctrl_usdhc1>;
        pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
        pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-       assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
-       assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD0>;
-       assigned-clock-rates = <0>, <176000000>;
        cd-gpios = <>;
        wp-gpios = <>;
        vmmc-supply = <>;
index bf8db20..4ea3d91 100644 (file)
        pinctrl-0 = <&pinctrl_usdhc2_8bit>;
        pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
        pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
-       assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
-       assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
-       assigned-clock-rates = <0>, <396000000>;
-       max-frequency = <132000000>;
        bus-width = <8>;
        non-removable;
        status = "okay";
index f350da3..d8b6706 100644 (file)
                         };
 
                        usdhc1: usdhc@02190000 {
-                               compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
+                               compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
                                reg = <0x02190000 0x4000>;
                                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_USDHC1>,
                                         <&clks IMX6UL_CLK_USDHC1>,
                                         <&clks IMX6UL_CLK_USDHC1>;
                                clock-names = "ipg", "ahb", "per";
+                               assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
+                               assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+                               assigned-clock-rates = <0>, <132000000>;
                                bus-width = <4>;
                                fsl,tuning-step= <2>;
                                status = "disabled";
                        };
 
                        usdhc2: usdhc@02194000 {
-                               compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
+                               compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
                                reg = <0x02194000 0x4000>;
                                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_USDHC2>,
                                         <&clks IMX6UL_CLK_USDHC2>,
                                         <&clks IMX6UL_CLK_USDHC2>;
                                clock-names = "ipg", "ahb", "per";
+                               assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+                               assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+                               assigned-clock-rates = <0>, <132000000>;
                                bus-width = <4>;
                                fsl,tuning-step= <2>;
                                status = "disabled";