To avoid potential division by zero in ipu_init_async_panel(),
let's check the di_clk rate prior to that.
Detected by CoverityScan, CID#56264 ("Division or modulo by zero")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit
d7777247e6ba4ca9fcc313bef6672060859fed19)
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Shrikant Bobade <Shrikant_Bobade@mentor.com>
(cherry picked from commit
739a8482f07187566ec8777dbd2d4b79a1056c49)
u32 div;
u32 di_clk = clk_get_rate(ipu->ipu_clk);
+ if (di_clk == 0) {
+ dev_err(ipu->dev, "di clock rate should not be zero\n");
+ return -EINVAL;
+ }
+
/* round up cycle_time, then calcalate the divider using scaled math */
cycle_time += (1000000000UL / di_clk) - 1;
div = (cycle_time * (di_clk / 256UL)) / (1000000000UL / 256UL);