MLK-14445-7 DTS: mx7ulp: Add PTA and PTB two GPIO banks

PTA and PTB banks are at M4 domain, but some boards like ARM2 use
them for controlling A7 domain modules. So we may need to support
them in GPIO driver.

In the imx_rgpio2p driver, the non-DM driver supports full 6 GPIO
banks, with PTA from index 0. But the DM driver which uses DTB only
have 4 GPIO banks, with PTC from index 0.

This will cause problem when using GPIO. So this patch add PTA and PTB
banks to DTB, and reorder the sequence for gpio with PTA from index 0.
So the non-DM driver and DM driver are aligned.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 0b4965271702d6a40047bd0c9b419dd007c03f35)
(cherry picked from commit 00a9e360416cf099a7697a375469d91cf63d5701)

diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
index 2efd8e9..0e2aea1 100644 (file)
--- a/arch/arm/dts/imx7ulp.dtsi
+++ b/arch/arm/dts/imx7ulp.dtsi
@@ -16,10 +16,12 @@
        interrupt-parent = <&intc>;
 
        aliases {
-               gpio0 = &gpio0;
-               gpio1 = &gpio1;
-               gpio2 = &gpio2;
-               gpio3 = &gpio3;
+               gpio0 = &gpio4;
+               gpio1 = &gpio5;
+               gpio2 = &gpio0;
+               gpio3 = &gpio1;
+               gpio4 = &gpio2;
+               gpio5 = &gpio3;
                mmc0 = &usdhc0;
                mmc1 = &usdhc1;
                serial0 = &lpuart4;
@@ -504,6 +506,22 @@
                        fsl,mux_mask = <0xf00>;
                };
 
+               gpio4: gpio@4103f000 {
+                       compatible = "fsl,imx7ulp-gpio";
+                       reg = <0x4103f000 0x1000 0x4100F000 0x40>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&iomuxc 0 0 32>;
+               };
+
+               gpio5: gpio@41040000 {
+                       compatible = "fsl,imx7ulp-gpio";
+                       reg = <0x41040000 0x1000 0x4100F040 0x40>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&iomuxc 0 32 32>;
+               };
+
                gpio0: gpio@40ae0000 {
                        compatible = "fsl,imx7ulp-gpio";
                        reg = <0x40ae0000 0x1000 0x400F0000 0x40>;