arm: ls1021aqds: Convert to driver model and enable serial support

Split duart configuration as device tree file. Move /chosen node
out of board commone device tree. Convert ls1021aqds nor and SD
configurations to driver model support (qspi already uses DM).
Enable ns16550 DM serial driver for nor configurations.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b574284..7af45bb 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -96,7 +96,7 @@ dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
 
-dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
+dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \
        ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
        fsl-ls2080a-rdb.dtb

diff --git a/arch/arm/dts/ls1021a-qds-duart.dts b/arch/arm/dts/ls1021a-qds-duart.dts
new file mode 100644 (file)
index 0000000..bc56867
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Freescale ls1021a QDS board common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a-qds.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &uart0;
+       };
+};

diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
deleted file mode 100644 (file)
index e634292..0000000
--- a/arch/arm/dts/ls1021a-qds.dts
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * Freescale ls1021a QDS board device tree source
- *
- * Copyright 2013-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/dts-v1/;
-#include "ls1021a.dtsi"
-
-/ {
-       model = "LS1021A QDS Board";
-
-       aliases {
-               enet0_rgmii_phy = &rgmii_phy1;
-               enet1_rgmii_phy = &rgmii_phy2;
-               enet2_rgmii_phy = &rgmii_phy3;
-               enet0_sgmii_phy = &sgmii_phy1c;
-               enet1_sgmii_phy = &sgmii_phy1d;
-               spi0 = &qspi;
-               spi1 = &dspi0;
-       };
-};
-
-&dspi0 {
-       bus-num = <0>;
-       status = "okay";
-
-       dspiflash: at45db021d@0 {
-               #address-cells = <1>;
-               #size-cells = <1>;
-               compatible = "atmel,dataflash";
-               spi-max-frequency = <16000000>;
-               spi-cpol;
-               spi-cpha;
-               reg = <0>;
-       };
-};
-
-&qspi {
-       bus-num = <0>;
-       status = "okay";
-
-       qflash0: s25fl128s@0 {
-               #address-cells = <1>;
-               #size-cells = <1>;
-               compatible = "spi-flash";
-               spi-max-frequency = <20000000>;
-               reg = <0>;
-       };
-};
-
-&i2c0 {
-       status = "okay";
-
-       pca9547: mux@77 {
-               reg = <0x77>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               i2c@0 {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       reg = <0x0>;
-
-                       ds3232: rtc@68 {
-                               compatible = "dallas,ds3232";
-                               reg = <0x68>;
-                               interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-                       };
-               };
-
-               i2c@2 {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       reg = <0x2>;
-
-                       ina220@40 {
-                               compatible = "ti,ina220";
-                               reg = <0x40>;
-                               shunt-resistor = <1000>;
-                       };
-
-                       ina220@41 {
-                               compatible = "ti,ina220";
-                               reg = <0x41>;
-                               shunt-resistor = <1000>;
-                       };
-               };
-
-               i2c@3 {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       reg = <0x3>;
-
-                       eeprom@56 {
-                               compatible = "atmel,24c512";
-                               reg = <0x56>;
-                       };
-
-                       eeprom@57 {
-                               compatible = "atmel,24c512";
-                               reg = <0x57>;
-                       };
-
-                       adt7461a@4c {
-                               compatible = "adi,adt7461a";
-                               reg = <0x4c>;
-                       };
-               };
-       };
-};
-
-&ifc {
-       #address-cells = <2>;
-       #size-cells = <1>;
-       /* NOR, NAND Flashes and FPGA on board */
-       ranges = <0x0 0x0 0x60000000 0x08000000
-                 0x2 0x0 0x7e800000 0x00010000
-                 0x3 0x0 0x7fb00000 0x00000100>;
-       status = "okay";
-
-       nor@0,0 {
-               #address-cells = <1>;
-               #size-cells = <1>;
-               compatible = "cfi-flash";
-               reg = <0x0 0x0 0x8000000>;
-               bank-width = <2>;
-               device-width = <1>;
-       };
-
-       fpga: board-control@3,0 {
-               #address-cells = <1>;
-               #size-cells = <1>;
-               compatible = "simple-bus";
-               reg = <0x3 0x0 0x0000100>;
-               bank-width = <1>;
-               device-width = <1>;
-               ranges = <0 3 0 0x100>;
-
-               mdio-mux-emi1 {
-                       compatible = "mdio-mux-mmioreg";
-                       mdio-parent-bus = <&mdio0>;
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       reg = <0x54 1>; /* BRDCFG4 */
-                       mux-mask = <0xe0>; /* EMI1[2:0] */
-
-                       /* Onboard PHYs */
-                       ls1021amdio0: mdio@0 {
-                               reg = <0>;
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               rgmii_phy1: ethernet-phy@1 {
-                                       reg = <0x1>;
-                               };
-                       };
-
-                       ls1021amdio1: mdio@20 {
-                               reg = <0x20>;
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               rgmii_phy2: ethernet-phy@2 {
-                                       reg = <0x2>;
-                               };
-                       };
-
-                       ls1021amdio2: mdio@40 {
-                               reg = <0x40>;
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               rgmii_phy3: ethernet-phy@3 {
-                                       reg = <0x3>;
-                               };
-                       };
-
-                       ls1021amdio3: mdio@60 {
-                               reg = <0x60>;
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               sgmii_phy1c: ethernet-phy@1c {
-                                       reg = <0x1c>;
-                               };
-                       };
-
-                       ls1021amdio4: mdio@80 {
-                               reg = <0x80>;
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               sgmii_phy1d: ethernet-phy@1d {
-                                       reg = <0x1d>;
-                               };
-                       };
-               };
-       };
-};
-
-&lpuart0 {
-       status = "okay";
-};
-
-&mdio0 {
-       tbi0: tbi-phy@8 {
-               reg = <0x8>;
-               device_type = "tbi-phy";
-       };
-};
-
-&uart0 {
-       status = "okay";
-};
-
-&uart1 {
-       status = "okay";
-};

diff --git a/arch/arm/dts/ls1021a-qds.dtsi b/arch/arm/dts/ls1021a-qds.dtsi
new file mode 100644 (file)
index 0000000..ca9e835
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds.dtsi
@@ -0,0 +1,215 @@
+/*
+ * Freescale ls1021a QDS board common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "ls1021a.dtsi"
+
+/ {
+       model = "LS1021A QDS Board";
+
+       aliases {
+               enet0_rgmii_phy = &rgmii_phy1;
+               enet1_rgmii_phy = &rgmii_phy2;
+               enet2_rgmii_phy = &rgmii_phy3;
+               enet0_sgmii_phy = &sgmii_phy1c;
+               enet1_sgmii_phy = &sgmii_phy1d;
+               spi0 = &qspi;
+               spi1 = &dspi0;
+       };
+};
+
+&dspi0 {
+       bus-num = <0>;
+       status = "okay";
+
+       dspiflash: at45db021d@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "atmel,dataflash";
+               spi-max-frequency = <16000000>;
+               spi-cpol;
+               spi-cpha;
+               reg = <0>;
+       };
+};
+
+&qspi {
+       bus-num = <0>;
+       status = "okay";
+
+       qflash0: s25fl128s@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+
+       pca9547: mux@77 {
+               reg = <0x77>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               i2c@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0>;
+
+                       ds3232: rtc@68 {
+                               compatible = "dallas,ds3232";
+                               reg = <0x68>;
+                               interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               i2c@2 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x2>;
+
+                       ina220@40 {
+                               compatible = "ti,ina220";
+                               reg = <0x40>;
+                               shunt-resistor = <1000>;
+                       };
+
+                       ina220@41 {
+                               compatible = "ti,ina220";
+                               reg = <0x41>;
+                               shunt-resistor = <1000>;
+                       };
+               };
+
+               i2c@3 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x3>;
+
+                       eeprom@56 {
+                               compatible = "atmel,24c512";
+                               reg = <0x56>;
+                       };
+
+                       eeprom@57 {
+                               compatible = "atmel,24c512";
+                               reg = <0x57>;
+                       };
+
+                       adt7461a@4c {
+                               compatible = "adi,adt7461a";
+                               reg = <0x4c>;
+                       };
+               };
+       };
+};
+
+&ifc {
+       #address-cells = <2>;
+       #size-cells = <1>;
+       /* NOR, NAND Flashes and FPGA on board */
+       ranges = <0x0 0x0 0x60000000 0x08000000
+                 0x2 0x0 0x7e800000 0x00010000
+                 0x3 0x0 0x7fb00000 0x00000100>;
+       status = "okay";
+
+       nor@0,0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "cfi-flash";
+               reg = <0x0 0x0 0x8000000>;
+               bank-width = <2>;
+               device-width = <1>;
+       };
+
+       fpga: board-control@3,0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               reg = <0x3 0x0 0x0000100>;
+               bank-width = <1>;
+               device-width = <1>;
+               ranges = <0 3 0 0x100>;
+
+               mdio-mux-emi1 {
+                       compatible = "mdio-mux-mmioreg";
+                       mdio-parent-bus = <&mdio0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x54 1>; /* BRDCFG4 */
+                       mux-mask = <0xe0>; /* EMI1[2:0] */
+
+                       /* Onboard PHYs */
+                       ls1021amdio0: mdio@0 {
+                               reg = <0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               rgmii_phy1: ethernet-phy@1 {
+                                       reg = <0x1>;
+                               };
+                       };
+
+                       ls1021amdio1: mdio@20 {
+                               reg = <0x20>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               rgmii_phy2: ethernet-phy@2 {
+                                       reg = <0x2>;
+                               };
+                       };
+
+                       ls1021amdio2: mdio@40 {
+                               reg = <0x40>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               rgmii_phy3: ethernet-phy@3 {
+                                       reg = <0x3>;
+                               };
+                       };
+
+                       ls1021amdio3: mdio@60 {
+                               reg = <0x60>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               sgmii_phy1c: ethernet-phy@1c {
+                                       reg = <0x1c>;
+                               };
+                       };
+
+                       ls1021amdio4: mdio@80 {
+                               reg = <0x80>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               sgmii_phy1d: ethernet-phy@1d {
+                                       reg = <0x1d>;
+                               };
+                       };
+               };
+       };
+};
+
+&lpuart0 {
+       status = "okay";
+};
+
+&mdio0 {
+       tbi0: tbi-phy@8 {
+               reg = <0x8>;
+               device_type = "tbi-phy";
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};

diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 2f16339..842f645 100644 (file)
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -1,7 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y

diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 6878df4..f4c81e2 100644 (file)
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -1,6 +1,10 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y

diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 0f740fd..2e98d6c 100644 (file)
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set

diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig
index 3249b48..e283f69 100644 (file)
--- a/configs/ls1021aqds_sdcard_defconfig
+++ b/configs/ls1021aqds_sdcard_defconfig
@@ -1,8 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index f6efc55..5bdc124 100644 (file)
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -375,7 +375,9 @@ unsigned long get_board_ddr_clk(void);
 #else
 #define CONFIG_CONS_INDEX              1
 #define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
+#endif
 #define CONFIG_SYS_NS16550_CLK         get_serial_clock()
 #endif