To improve the performance, enable the bank interleave for LPDDR3. Update
the LPDDR3 settings to new script IMX7D_LPDDR3_533MHz_2GB_32bit_V2.0.ds5.
Changes:
1. Enable bank interleave
2. Improve the drive strength for non-TO1.1 chips.
3. Updates ZQ_CON0 settings.
4. Change to 0 for reserved bits.
File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=
233861153&objAction=browse&sort=name&viewType=1
Test:
Passed stress test on one 19x19 lpddr3 arm2 and one 12x12 lpddr3 arm2.
Passed LPSR test on one 12x12 lpddr3 arm2.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit
9a4fa3f8d2762791a76fd90e83feec8c8c9235b0)
DATA 4 0x307a01a8 0x80100004
DATA 4 0x307a0200 0x00000016
-DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0204 0x00090909
DATA 4 0x307a0210 0x00000f00
-DATA 4 0x307a0214 0x05050505
-DATA 4 0x307a0218 0x0f0f0505
+DATA 4 0x307a0214 0x08080808
+DATA 4 0x307a0218 0x0f0f0808
-DATA 4 0x307a0240 0x06000601
+DATA 4 0x307a0240 0x06000600
DATA 4 0x307a0244 0x00000000
DATA 4 0x30391000 0x00000000
DATA 4 0x30790000 0x17421e40
DATA 4 0x307900b0 0x1010007e
DATA 4 0x3079001C 0x01010000
-DATA 4 0x3079009c 0x0db60d6e
+DATA 4 0x3079009c 0x00000b24
DATA 4 0x30790030 0x06060606
DATA 4 0x30790020 0x0a0a0a0a
DATA 4 0x30790050 0x01000008
DATA 4 0x30790050 0x00000008
DATA 4 0x30790018 0x0000000f
-DATA 4 0x307900c0 0x1e487304
-DATA 4 0x307900c0 0x1e487304
-DATA 4 0x307900c0 0x1e487306
-DATA 4 0x307900c0 0x1e4c7304
+DATA 4 0x307900c0 0x0e487304
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e4c7306
CHECK_BITS_SET 4 0x307900c4 0x1
-DATA 4 0x307900c0 0x1e487304
+DATA 4 0x307900c0 0x0e487304
DATA 4 0x30384130 0x00000000
DATA 4 0x30340020 0x00000178
DATA 4 0x307a01a8 0x80100004
DATA 4 0x307a0200 0x00000016
-DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0204 0x00090909
DATA 4 0x307a0210 0x00000f00
-DATA 4 0x307a0214 0x05050505
-DATA 4 0x307a0218 0x0f0f0505
+DATA 4 0x307a0214 0x08080808
+DATA 4 0x307a0218 0x0f0f0808
DATA 4 0x307a0240 0x06000601
DATA 4 0x307a0244 0x00000000
str r7, [r3, r6]
ldr r6, =0x204
- ldr r7, =0x00171717
+ ldr r7, =0x00090909
str r7, [r3, r6]
ldr r6, =0x210
str r7, [r3, r6]
ldr r6, =0x214
- ldr r7, =0x05050505
+ ldr r7, =0x08080808
str r7, [r3, r6]
ldr r6, =0x218
- ldr r7, =0x0F0F0505
+ ldr r7, =0x0f0f0808
str r7, [r3, r6]
ldr r6, =0x240
- ldr r7, =0x06000601
+ ldr r7, =0x06000600
str r7, [r3, r6]
ldr r6, =0x244
ldr r7, =0x30303030
str r7, [r4, r6]
-4:
ldr r6, =0x1c
ldr r7, =0x01010000
str r7, [r4, r6]
ldr r7, =0x0DB60D6E
str r7, [r4, r6]
+ b 5f
+
+4:
+ ldr r6, =0x1c
+ ldr r7, =0x01010000
+ str r7, [r4, r6]
+
+ ldr r6, =0x9c
+ ldr r7, =0x00000b24
+ str r7, [r4, r6]
+
+5:
ldr r6, =0x20
ldr r7, =0x0a0a0a0a
str r7, [r4, r6]
str r7, [r4, r6]
ldr r6, =0xc0
- ldr r7, =0x0e407304
+ ldr r7, =0x0e487304
str r7, [r4, r6]
ldr r6, =0xc0
- ldr r7, =0x0e447304
+ ldr r7, =0x0e4c7304
str r7, [r4, r6]
ldr r6, =0xc0
- ldr r7, =0x0e447306
+ ldr r7, =0x0e4c7306
str r7, [r4, r6]
- ldr r6, =0xc0
- ldr r7, =0x0e4c7304
- str r7, [r4, r6]
+6:
+ ldr r7, [r4, #0xc4]
+ tst r7, #0x1
+ beq 6b
ldr r6, =0xc0
- ldr r7, =0x0e487306
+ ldr r7, =0x0e487304
str r7, [r4, r6]
ldr r7, =0x0
ldr r1, =0x00000016
str r1, [r0, #0x200]
- ldr r1, =0x00171717
+ ldr r1, =0x00090909
str r1, [r0, #0x204]
ldr r1, =0x00000f00
str r1, [r0, #0x210]
- ldr r1, =0x05050505
+ ldr r1, =0x08080808
str r1, [r0, #0x214]
- ldr r1, =0x0f0f0505
+ ldr r1, =0x0f0f0808
str r1, [r0, #0x218]
- ldr r1, =0x06000601
+ ldr r1, =0x06000600
str r1, [r0, #0x240]
mov r1, #0x0
str r1, [r0, #0x244]
str r1, [r0, #0xb0]
ldr r1, =0x01010000
str r1, [r0, #0x1c]
+
+ ldr r2, =ANATOP_BASE_ADDR
+ ldr r3, [r2, #0x800]
+ and r3, r3, #0xFF
+ cmp r3, #0x11
+ bne 17f
+
ldr r1, =0x0db60d6e
str r1, [r0, #0x9c]
-
+ b 18f
+17:
+ ldr r1, =0x00000b24
+ str r1, [r0, #0x9c]
+18:
ldr r1, =0x06060606
str r1, [r0, #0x30]
ldr r1, =0x0a0a0a0a
ldr r1, =0x0000000f
str r1, [r0, #0x18]
- ldr r1, =0x1e487304
- str r1, [r0, #0xc0]
- ldr r1, =0x1e487304
+ ldr r1, =0x0e487304
str r1, [r0, #0xc0]
- ldr r1, =0x1e487306
+ ldr r1, =0x0e4c7304
str r1, [r0, #0xc0]
- ldr r1, =0x1e4c7304
+ ldr r1, =0x0e4c7306
str r1, [r0, #0xc0]
wait_zq:
tst r1, #0x1
beq wait_zq
- ldr r1, =0x1e487304
+ ldr r1, =0x0e487304
str r1, [r0, #0xc0]
ldr r0, =CCM_BASE_ADDR
DATA 4 0x307a01a8 0x80100004
DATA 4 0x307a0200 0x00000016
-DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0204 0x00090909
DATA 4 0x307a0210 0x00000f00
-DATA 4 0x307a0214 0x05050505
-DATA 4 0x307a0218 0x0f0f0505
+DATA 4 0x307a0214 0x08080808
+DATA 4 0x307a0218 0x0f0f0808
-DATA 4 0x307a0240 0x06000601
+DATA 4 0x307a0240 0x06000600
DATA 4 0x307a0244 0x00000000
DATA 4 0x30391000 0x00000000
DATA 4 0x30790000 0x17421e40
DATA 4 0x307900b0 0x1010007e
DATA 4 0x3079001C 0x01010000
-DATA 4 0x3079009c 0x0db60d6e
+DATA 4 0x3079009c 0x00000b24
DATA 4 0x30790030 0x06060606
DATA 4 0x30790020 0x0a0a0a0a
DATA 4 0x30790050 0x01000008
DATA 4 0x30790050 0x00000008
DATA 4 0x30790018 0x0000000f
-DATA 4 0x307900c0 0x1e487304
-DATA 4 0x307900c0 0x1e487304
-DATA 4 0x307900c0 0x1e487306
-DATA 4 0x307900c0 0x1e4c7304
+DATA 4 0x307900c0 0x0e487304
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e4c7306
CHECK_BITS_SET 4 0x307900c4 0x1
-DATA 4 0x307900c0 0x1e487304
+DATA 4 0x307900c0 0x0e487304
DATA 4 0x30384130 0x00000000
DATA 4 0x30340020 0x00000178
DATA 4 0x307a01a8 0x80100004
DATA 4 0x307a0200 0x00000016
-DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0204 0x00090909
DATA 4 0x307a0210 0x00000f00
-DATA 4 0x307a0214 0x05050505
-DATA 4 0x307a0218 0x0f0f0505
+DATA 4 0x307a0214 0x08080808
+DATA 4 0x307a0218 0x0f0f0808
DATA 4 0x307a0240 0x06000601
DATA 4 0x307a0244 0x00000000
ldr r1, =0x00000016
str r1, [r0, #0x200]
- ldr r1, =0x00171717
+ ldr r1, =0x00090909
str r1, [r0, #0x204]
ldr r1, =0x00000f00
str r1, [r0, #0x210]
- ldr r1, =0x05050505
+ ldr r1, =0x08080808
str r1, [r0, #0x214]
- ldr r1, =0x0f0f0505
+ ldr r1, =0x0f0f0808
str r1, [r0, #0x218]
- ldr r1, =0x06000601
+ ldr r1, =0x06000600
str r1, [r0, #0x240]
mov r1, #0x0
str r1, [r0, #0x244]
str r1, [r0, #0xb0]
ldr r1, =0x01010000
str r1, [r0, #0x1c]
+
+ ldr r2, =ANATOP_BASE_ADDR
+ ldr r3, [r2, #0x800]
+ and r3, r3, #0xFF
+ cmp r3, #0x11
+ bne 1f
+
ldr r1, =0x0db60d6e
str r1, [r0, #0x9c]
-
+ b 2f
+1:
+ ldr r1, =0x00000b24
+ str r1, [r0, #0x9c]
+2:
ldr r1, =0x06060606
str r1, [r0, #0x30]
ldr r1, =0x0a0a0a0a
ldr r1, =0x0000000f
str r1, [r0, #0x18]
- ldr r1, =0x1e487304
- str r1, [r0, #0xc0]
- ldr r1, =0x1e487304
+ ldr r1, =0x0e487304
str r1, [r0, #0xc0]
- ldr r1, =0x1e487306
+ ldr r1, =0x0e4c7304
str r1, [r0, #0xc0]
- ldr r1, =0x1e4c7304
+ ldr r1, =0x0e4c7306
str r1, [r0, #0xc0]
wait_zq:
tst r1, #0x1
beq wait_zq
- ldr r1, =0x1e487304
+ ldr r1, =0x0e487304
str r1, [r0, #0xc0]
ldr r0, =CCM_BASE_ADDR