arm64: dts: imx8qm-lpddr4-val: support audio sound card

Add support audio sound card (ESAI/ASRC/AMIX/CS42888/MQS)

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 03cd638..c1073c6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -53,7 +53,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \
                          imx8qm-mek-enet2-tja1100.dtb imx8qm-mek-rpmsg.dtb \
                          imx8qm-mek-hdmi.dtb imx8qm-mek-dsp.dtb \
-                         imx8qm-lpddr4-val.dtb
+                         imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \
+                         imx8qm-lpddr4-val-spdif.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640.dtb \

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts
new file mode 100644 (file)
index 0000000..13f670f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "imx8qm-lpddr4-val.dts"
+
+/ {
+       sound-cs42888 {
+               status = "disabled";
+       };
+
+       sound-spdif {
+               compatible = "fsl,imx-audio-spdif";
+               model = "imx-spdif";
+               spdif-controller = <&spdif0>;
+               spdif-in;
+               spdif-out;
+               status = "disabled";
+       };
+
+       sound-mqs {
+               compatible = "fsl,imx8qm-lpddr4-arm2-mqs",
+                               "fsl,imx-audio-mqs";
+               model = "mqs-audio";
+               audio-cpu = <&sai1>;
+               audio-codec = <&mqs>;
+               audio-asrc = <&asrc1>;
+       };
+};
+
+&esai0 {
+       status = "disabled";
+};
+
+&iomuxc {
+       pinctrl_spdif0: spdif0grp {
+               fsl,pins = <
+                       IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX  0xc6000040
+                       IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX  0xc6000040
+               >;
+       };
+
+       pinctrl_mqs: mqsgrp {
+               fsl,pins = <
+                       IMX8QM_SPDIF0_TX_AUD_MQS_L      0xc6000061
+                       IMX8QM_SPDIF0_RX_AUD_MQS_R      0xc6000061
+               >;
+       };
+};
+
+&mqs {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_mqs>;
+       status = "okay";
+};
+
+&spdif0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_spdif0>;
+       status = "disabled";
+};
+
+&sai1 {
+       assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
+       assigned-clock-rates = <786432000>, <49152000>, <24576000>;
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts
new file mode 100644 (file)
index 0000000..75e8fdf
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "imx8qm-lpddr4-val.dts"
+
+/ {
+       sound-cs42888 {
+               status = "disabled";
+       };
+
+       sound-spdif {
+               compatible = "fsl,imx-audio-spdif";
+               model = "imx-spdif";
+               spdif-controller = <&spdif0>;
+               spdif-in;
+               spdif-out;
+       };
+
+       sound-mqs {
+               compatible = "fsl,imx8qm-lpddr4-arm2-mqs",
+                               "fsl,imx-audio-mqs";
+               model = "mqs-audio";
+               audio-cpu = <&sai1>;
+               audio-codec = <&mqs>;
+               status = "disabled";
+       };
+};
+
+&esai0 {
+       status = "disabled";
+};
+
+&iomuxc {
+       pinctrl_spdif0: spdif0grp {
+               fsl,pins = <
+                       IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX  0xc6000040
+                       IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX  0xc6000040
+               >;
+       };
+
+       pinctrl_mqs: mqsgrp {
+               fsl,pins = <
+                       IMX8QM_SPDIF0_TX_AUD_MQS_L      0xc6000061
+                       IMX8QM_SPDIF0_RX_AUD_MQS_R      0xc6000061
+               >;
+       };
+};
+
+&esai0 {
+       status = "disabled";
+};
+
+&mqs {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_mqs>;
+       status = "disabled";
+};
+
+&spdif0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_spdif0>;
+       assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
+       assigned-clock-rates = <786432000>, <49152000>, <24576000>;
+       status = "okay";
+};
+
+&sai1 {
+       assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
+       assigned-clock-rates = <786432000>, <49152000>, <24576000>;
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts
index bda23bc..eef37c8 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts
@@ -98,6 +98,172 @@
                gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
                enable-active-high;
        };
+
+       reg_audio: regulator@0 {
+               compatible = "regulator-fixed";
+               regulator-name = "cs42888_supply";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+
+       sound-cs42888 {
+               compatible = "fsl,imx8qm-sabreauto-cs42888",
+                               "fsl,imx-audio-cs42888";
+               model = "imx-cs42888";
+               audio-cpu = <&esai0>;
+               audio-codec = <&cs42888>;
+               audio-asrc = <&asrc0>;
+               audio-routing =
+                       "Line Out Jack", "AOUT1L",
+                       "Line Out Jack", "AOUT1R",
+                       "Line Out Jack", "AOUT2L",
+                       "Line Out Jack", "AOUT2R",
+                       "Line Out Jack", "AOUT3L",
+                       "Line Out Jack", "AOUT3R",
+                       "Line Out Jack", "AOUT4L",
+                       "Line Out Jack", "AOUT4R",
+                       "AIN1L", "Line In Jack",
+                       "AIN1R", "Line In Jack",
+                       "AIN2L", "Line In Jack",
+                       "AIN2R", "Line In Jack";
+       };
+};
+
+&amix {
+       status = "okay";
+};
+
+&asrc0 {
+       assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
+       assigned-clock-rates = <786432000>, <49152000>, <24576000>;
+       fsl,asrc-rate  = <48000>;
+       status = "okay";
+};
+
+&asrc1 {
+       fsl,asrc-rate = <48000>;
+       assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
+       assigned-clock-rates = <786432000>, <49152000>, <24576000>;
+
+       status = "okay";
+};
+
+&esai0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esai0>;
+       assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+                       <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+                       <&esai0_lpcg 0>;
+       assigned-clock-parents = <&aud_pll_div0_lpcg 0>;
+       assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
+       status = "okay";
+};
+
+&sai6 {
+       assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
+                       <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
+                       <&sai6_lpcg 0>;
+       assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
+       assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>;
+       fsl,sai-asynchronous;
+       fsl,txm-rxs;
+       status = "okay";
+};
+
+&sai7 {
+       assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
+                       <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
+                       <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
+                       <&sai7_lpcg 0>;
+       assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
+       assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>;
+       fsl,sai-asynchronous;
+       fsl,txm-rxs;
+       status = "okay";
+};
+
+&i2c0 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpi2c0>;
+       clock-frequency = <100000>;
+       status = "okay";
+
+       cs42888: cs42888@48 {
+               compatible = "cirrus,cs42888";
+               reg = <0x48>;
+               clocks = <&mclkout0_lpcg 0>;
+               clock-names = "mclk";
+               VA-supply = <&reg_audio>;
+               VD-supply = <&reg_audio>;
+               VLS-supply = <&reg_audio>;
+               VLC-supply = <&reg_audio>;
+               reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>;
+               power-domains = <&pd IMX_SC_R_MCLK_OUT_0>,
+                               <&pd IMX_SC_R_AUDIO_CLK_0>,
+                               <&pd IMX_SC_R_AUDIO_CLK_1>,
+                               <&pd IMX_SC_R_AUDIO_PLL_0>,
+                               <&pd IMX_SC_R_AUDIO_PLL_1>;
+               power-domain-names = "pd_mclk_out_0",
+                                       "pd_audio_clk_0",
+                                       "pd_audio_clk_1",
+                                       "pd_audio_clk_0",
+                                       "pd_audio_clk_1";
+               assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+                               <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+                               <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+                               <&mclkout0_lpcg 0>;
+               assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>;
+               status = "okay";
+       };
+};
+
+&i2c1 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpi2c1>;
+       status = "okay";
+
+       pca9557_a: gpio@18 {
+               compatible = "nxp,pca9557";
+               reg = <0x18>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       pca9557_b: gpio@19 {
+               compatible = "nxp,pca9557";
+               reg = <0x19>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       pca9557_c: gpio@1b {
+               compatible = "nxp,pca9557";
+               reg = <0x1b>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       pca9557_d: gpio@1f {
+               compatible = "nxp,pca9557";
+               reg = <0x1f>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
 };
 
 &lpuart0 {
@@ -164,6 +330,22 @@
 &iomuxc {
        pinctrl-names = "default";
 
+       pinctrl_esai0: esai0grp {
+               fsl,pins = <
+                       IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR                          0xc6000040
+                       IMX8QM_ESAI0_FST_AUD_ESAI0_FST                          0xc6000040
+                       IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR                        0xc6000040
+                       IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT                        0xc6000040
+                       IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0                          0xc6000040
+                       IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1                          0xc6000040
+                       IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3                  0xc6000040
+                       IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2                  0xc6000040
+                       IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1                  0xc6000040
+                       IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0                  0xc6000040
+                       IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0                      0xc6000040
+               >;
+       };
+
        pinctrl_fec1: fec1grp {
                fsl,pins = <
                        IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD             0x000014a0
@@ -184,6 +366,20 @@
                >;
        };
 
+       pinctrl_lpi2c0: lpi2c0grp {
+               fsl,pins = <
+                       IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL                     0xc600004c
+                       IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA                     0xc600004c
+               >;
+       };
+
+       pinctrl_lpi2c1: lpi2c1grp {
+               fsl,pins = <
+                       IMX8QM_GPT0_CLK_DMA_I2C1_SCL                            0xc600004c
+                       IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA                        0xc600004c
+               >;
+       };
+
        pinctrl_lpuart0: lpuart0grp {
                fsl,pins = <
                        IMX8QM_UART0_RX_DMA_UART0_RX                            0x06000020