MLK-15110-22 drm/imx: dpu: crtc: Evade the first dumb frame for DPR/PRG errata

To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame
which is generated by DPU.  The way we achieve that is to bypass TCON(but set
the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU
display controller, and then enable the display controller, wait for the frame
index starting to move and finally switch TCON to operation mode.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

diff --git a/drivers/gpu/drm/imx/dpu/dpu-crtc.c b/drivers/gpu/drm/imx/dpu/dpu-crtc.c
index 5e5202f..04e7470 100644 (file)
--- a/drivers/gpu/drm/imx/dpu/dpu-crtc.c
+++ b/drivers/gpu/drm/imx/dpu/dpu-crtc.c
@@ -127,6 +127,14 @@ static void dpu_crtc_enable(struct drm_crtc *crtc)
 
                crtc->state->event = NULL;
        }
+
+       /*
+        * TKT320590:
+        * Turn TCON into operation mode later after the first dumb frame is
+        * generated by DPU.  This makes DPR/PRG be able to evade the frame.
+        */
+       framegen_wait_for_frame_counter_moving(dpu_crtc->fg);
+       tcon_set_operation_mode(dpu_crtc->tcon);
 }
 
 static void dpu_crtc_disable(struct drm_crtc *crtc)

diff --git a/drivers/gpu/imx/dpu/dpu-tcon.c b/drivers/gpu/imx/dpu/dpu-tcon.c
index eb76df3..a0a94ce 100644 (file)
--- a/drivers/gpu/imx/dpu/dpu-tcon.c
+++ b/drivers/gpu/imx/dpu/dpu-tcon.c
@@ -110,7 +110,8 @@ int tcon_set_fmt(struct dpu_tcon *tcon, u32 bus_format)
 }
 EXPORT_SYMBOL_GPL(tcon_set_fmt);
 
-void tcon_cfg_videomode(struct dpu_tcon *tcon, struct drm_display_mode *m)
+/* This function is used to workaround TKT320590 which is related to DPR/PRG. */
+void tcon_set_operation_mode(struct dpu_tcon *tcon)
 {
        u32 val;
 
@@ -118,6 +119,23 @@ void tcon_cfg_videomode(struct dpu_tcon *tcon, struct drm_display_mode *m)
        val = dpu_tcon_read(tcon, TCON_CTRL);
        val &= ~BYPASS;
        dpu_tcon_write(tcon, val, TCON_CTRL);
+       mutex_unlock(&tcon->mutex);
+}
+EXPORT_SYMBOL_GPL(tcon_set_operation_mode);
+
+void tcon_cfg_videomode(struct dpu_tcon *tcon, struct drm_display_mode *m)
+{
+       u32 val;
+
+       mutex_lock(&tcon->mutex);
+       /*
+        * TKT320590:
+        * Turn TCON into operation mode later after the first dumb frame is
+        * generated by DPU.  This makes DPR/PRG be able to evade the frame.
+        */
+       val = dpu_tcon_read(tcon, TCON_CTRL);
+       val |= BYPASS;
+       dpu_tcon_write(tcon, val, TCON_CTRL);
 
        /* dsp_control[0]: hsync */
        dpu_tcon_write(tcon, X(m->hsync_start), SPGPOSON(0));

diff --git a/include/video/dpu.h b/include/video/dpu.h
index 6694379..5e04432 100644 (file)
--- a/include/video/dpu.h
+++ b/include/video/dpu.h
@@ -653,6 +653,7 @@ void dpu_lb_put(struct dpu_layerblend *lb);
 /* Timing Controller Unit */
 struct dpu_tcon;
 int tcon_set_fmt(struct dpu_tcon *tcon, u32 bus_format);
+void tcon_set_operation_mode(struct dpu_tcon *tcon);
 void tcon_cfg_videomode(struct dpu_tcon *tcon, struct drm_display_mode *m);
 struct dpu_tcon *dpu_tcon_get(struct dpu_soc *dpu, int id);
 void dpu_tcon_put(struct dpu_tcon *tcon);