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SEC 4 Device Tree Binding
Copyright (C) 2008-2011 Freescale Semiconductor Inc.
+Copyright 2017 NXP
CONTENTS
-Overview
-Run Time Integrity Check (RTIC) Memory Node
-Secure Non-Volatile Storage (SNVS) Node
-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
+ -CAAM Secure Memory Storage Interface
-Full Example
NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
Definition: A list of clock name strings in the same order as the
clocks property.
+ - first-jr-index
+ Usage: required only for i.MX8QM and i.MX8QXP
+ Value type: <u32>
+ Definition: Specifies the first job ring index assigned to kernel
+ to read aliased register since CAAM page 0 is not accessible.
+
Note: All other standard properties (see the ePAPR) are allowed
but are optional.
wakeup-source;
};
+=====================================================================
+CAAM Secure Memory Storage Interface
+
+ A CAAM-SM child node that defines Secure Memory.
+
+ - compatible
+ Usage: required
+ Value type: <string>
+ Definition: Must include "fsl,imx6q-caam-sm".
+
+ - regmap
+ Usage: required
+ Value type: <phandle>
+ Definition: this is phandle to the register map node.
+
+EXAMPLE
+ caam_sm: caam-sm@31800000 {
+ compatible = "fsl,imx6q-caam-sm";
+ reg = <0 0x31800000 0 0x1ffff>;
+ };
+
=====================================================================
FULL EXAMPLE
};
};
+ caam_sm: caam-sm@31800000 {
+ compatible = "fsl,imx6q-caam-sm";
+ reg = <0 0x31800000 0 0x1ffff>;
+ };
+
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