Default frequency is
786432000 and we cannot derive an exact bitclk
for 24 bits tests.
This is similar with commit
9e3c04a3e9222a ("MLK-14781-2: ARM: dts: change
audio pll frequency for ssi master mode").
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
};
&ssi2 {
+ assigned-clocks = <&clks IMX6SX_CLK_PLL4>,
+ <&clks IMX6SX_PLL4_BYPASS>,
+ <&clks IMX6SX_CLK_SSI2_SEL>;
+ assigned-clock-parents = <&clks IMX6SX_CLK_OSC>,
+ <&clks IMX6SX_CLK_PLL4>,
+ <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <1179648000>, <0>, <0>;
status = "okay";
};