{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+ u8 channels = substream->runtime->channels;
u32 xcsr, count = 100;
+ int i;
/*
* Asynchronous mode: Clear SYNC for both Tx and Rx.
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
+ for (i = 0; tx && i < channels; i++)
+ regmap_write(sai->regmap, FSL_SAI_TDR, 0x0);
+ if (tx)
+ udelay(10);
+
regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
regmap_update_bits(sai->regmap, FSL_SAI_TCSR,