MLK-16204-3: clk: imx8mq: add ocotp clock

Add OCOTP clock support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
index d37db2e..a6c2353 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
@@ -400,7 +400,11 @@
 
        ocotp: ocotp-ctrl@30350000 {
                compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
-               reg = <0x0 0x30350000 0x0 0x10000>;
+               reg = <0 0x30350000 0 0x10000>;
+               clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
+               /* For nvmem subnodes */
+               #address-cells = <1>;
+               #size-cells = <1>;
        };
 
        anatop: anatop@30360000 {

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 38cafa6..2728aad 100644 (file)
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -763,6 +763,7 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
        clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2_div", base + 0x4180, 0);
        clks[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3_div", base + 0x4190, 0);
        clks[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4_div", base + 0x41a0, 0);
+       clks[IMX8MQ_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
        clks[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl_div", base + 0x4250, 0);
        clks[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_gate4("pcie2_root_clk", "pcie2_ctrl_div", base + 0x4640, 0);
        clks[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1_div", base + 0x4280, 0);

diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 1c431d0..1e8c349 100644 (file)
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -613,5 +613,7 @@
 #define IMX8MQ_CLK_DISP_APB_ROOT               477
 #define IMX8MQ_CLK_DISP_RTRM_ROOT              478
 
-#define IMX8MQ_CLK_END                         479
+#define IMX8MQ_CLK_OCOTP_ROOT                  479
+
+#define IMX8MQ_CLK_END                         480
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */