LF-3503 ARM64: imx8mp-ddr4-evk: add nand support

Add nand support for i.MX8MP-DDR4-EVK board.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Han Xu <han.xu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts
index 0ec1cb4..54122d6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts
@@ -7,6 +7,10 @@
 
 / {
        model = "NXP i.MX8MPlus DDR4 EVK board";
+
+       gpio-leds {
+               status = "disabled";
+       };
 };
 
 &flexspi {
@@ -28,6 +32,13 @@
                               <2079000000>;
 };
 
+&gpmi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpmi_nand>;
+       status = "okay";
+       nand-on-flash-bbt;
+};
+
 &gpu_2d {
        assigned-clocks = <&clk IMX8MP_CLK_GPU2D_SRC>,
                          <&clk IMX8MP_CLK_GPU_AXI>,
@@ -93,3 +104,28 @@
        thres-high = <3 3>;             /* (FIFO * 3 / 3) */
        status = "okay";
 };
+
+&iomuxc {
+       pinctrl_gpmi_nand: gpmi-nand {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_ALE__NAND_ALE                 0x00000096
+                       MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B             0x00000096
+                       MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B             0x00000096
+                       MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B             0x00000096
+                       MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B             0x00000096
+                       MX8MP_IOMUXC_NAND_CLE__NAND_CLE                 0x00000096
+                       MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00           0x00000096
+                       MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01           0x00000096
+                       MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02           0x00000096
+                       MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03           0x00000096
+                       MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04           0x00000096
+                       MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05           0x00000096
+                       MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06           0x00000096
+                       MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07           0x00000096
+                       MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B               0x00000096
+                       MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B         0x00000056
+                       MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B               0x00000096
+                       MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B               0x00000096
+               >;
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 3bf51db..bf3daad 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -2081,6 +2081,35 @@
                        };
                };
 
+               dma_apbh: dma-apbh@33000000 {
+                       compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+                       reg = <0x33000000 0x2000>;
+                       interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+                       #dma-cells = <1>;
+                       dma-channels = <4>;
+                       clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+               };
+
+               gpmi: gpmi-nand@33002000{
+                       compatible = "fsl,imx7d-gpmi-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+                       reg-names = "gpmi-nand", "bch";
+                       interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "bch";
+                       clocks = <&clk IMX8MP_CLK_NAND_ROOT>,
+                               <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+                       clock-names = "gpmi_io", "gpmi_bch_apb";
+                       dmas = <&dma_apbh 0>;
+                       dma-names = "rx-tx";
+                       status = "disabled";
+               };
+
                pcie: pcie@33800000 {
                        compatible = "fsl,imx8mp-pcie", "snps,dw-pcie";
                        reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;