MLK-11698 ARM: imx: correct stop_mode_config bit offset

STOP_MODE_CONFIG field of PMU_MISC0 register are different
on different i.MX6 SoC, weak2P5 can only be enabled when
STOP_MODE_CONFIG is clear, need to read STOP_MODE_CONFIG
setting before enabling weak2P5, so the register field
must be correct, the definition are as below:

i.MX6Q/DL: bit[12];
i.MX6SL: bit[12:11], but only bit[11] is valid, so use bit[11];
i.MX6SX/UL: bit[11:10].

Signed-off-by: Anson Huang <b20788@freescale.com>

diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 7f1e936..735749e 100644 (file)
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -41,6 +41,8 @@
 #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN      0x8
 #define BM_ANADIG_REG_CORE_FET_ODRIVE          0x20000000
 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG   0x1000
+#define BM_ANADIG_ANA_MISC0_V2_STOP_MODE_CONFIG        0x800
+#define BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG        0xc00
 /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
 #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS   0x2000
 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B   0x80000
@@ -50,14 +52,20 @@ static struct regmap *anatop;
 
 static void imx_anatop_enable_weak2p5(bool enable)
 {
-       u32 reg, val;
+       u32 reg, val, mask;
 
        regmap_read(anatop, ANADIG_ANA_MISC0, &val);
 
+       if (cpu_is_imx6sx() || cpu_is_imx6ul())
+               mask = BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG;
+       else if (cpu_is_imx6sl())
+               mask = BM_ANADIG_ANA_MISC0_V2_STOP_MODE_CONFIG;
+       else
+               mask = BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG;
+
        /* can only be enabled when stop_mode_config is clear. */
        reg = ANADIG_REG_2P5;
-       reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
-               REG_SET : REG_CLR;
+       reg += (enable && (val & mask) == 0) ? REG_SET : REG_CLR;
        regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
 }