arm64: dts: imx8qm imx8qxp: enable mailbox for vpu

- The mailbox of mu_m0 is used by vpu decoder
- The mailbox of mu1_m0 and mu2_m0 are used by vpu encoder
  mu2_m0 only enabled on imx8qm

Signed-off-by: Shijie Qin <shijie.qin@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
index dea779a..96787fb 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
@@ -22,8 +22,14 @@ vpu_subsys: bus@2c000000 {
                reg = <0x2c000000 0x1000000>;
                reg-names = "vpu_regs";
                power-domains = <&pd IMX_SC_R_VPU_DEC_0>,
-                               <&pd IMX_SC_R_VPU>, <&pd IMX_SC_R_VPU_MU_0>;
-               power-domain-names = "vpudec", "vpu", "vpumu0";
+                               <&pd IMX_SC_R_VPU>;
+               power-domain-names = "vpudec", "vpu";
+
+               mbox-names = "tx0", "tx1", "rx";
+               mboxes = <&mu_m0 0 0
+                         &mu_m0 0 1
+                         &mu_m0 1 0>;
+
                status = "disabled";
        };
 
@@ -33,34 +39,43 @@ vpu_subsys: bus@2c000000 {
                        <0x2c000000 0x2000000>; /*VPU*/
                reg-names = "vpu_regs";
                power-domains = <&pd IMX_SC_R_VPU_ENC_0>,
-                               <&pd IMX_SC_R_VPU>, <&pd IMX_SC_R_VPU_MU_1>;
-               power-domain-names = "vpuenc1", "vpu", "vpumu1";
+                               <&pd IMX_SC_R_VPU>;
+               power-domain-names = "vpuenc1", "vpu";
                #address-cells = <1>;
                #size-cells = <1>;
                status = "disabled";
        };
 
-       mu_m0: mu_m0@2d000000 {
-               compatible = "fsl,imx8-mu0-vpu-m0";
+       mu_m0: mailbox@2d000000 {
+               compatible = "fsl,imx8-mu0-vpu-m0", "fsl,imx6sx-mu";
                reg = <0x2d000000 0x20000>;
                interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+               #mbox-cells = <2>;
+               power-domains = <&pd IMX_SC_R_VPU_MU_0>;
+               power-domain-names = "vpumu0";
                fsl,vpu_ap_mu_id = <16>;
                status = "okay";
        };
 
-       mu1_m0: mu1_m0@2d020000 {
-               compatible = "fsl,imx8-mu1-vpu-m0";
+       mu1_m0: mailbox@2d020000 {
+               compatible = "fsl,imx8-mu1-vpu-m0", "fsl,imx6sx-mu";
                reg = <0x2d020000 0x20000>;
                interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
                fsl,vpu_ap_mu_id = <17>;
+               #mbox-cells = <2>;
+               power-domains = <&pd IMX_SC_R_VPU_MU_1>;
+               power-domain-names = "vpumu1";
                status = "okay";
        };
 
-       mu2_m0: mu2_m0@2d040000 {
-               compatible = "fsl,imx8-mu2-vpu-m0";
+       mu2_m0: mailbox@2d040000 {
+               compatible = "fsl,imx8-mu2-vpu-m0", "fsl,imx6sx-mu";
                reg = <0x2d040000 0x20000>;
                interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
                fsl,vpu_ap_mu_id = <18>;
+               #mbox-cells = <2>;
+               power-domains = <&pd IMX_SC_R_VPU_MU_2>;
+               power-domain-names = "vpumu2";
                status = "disabled";
        };
 };

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index b8ad2be..0d25dcf 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -1330,8 +1330,16 @@
        resolution-max = <1920 1080>;
        fps-max = <120>;
        power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>,
-                       <&pd IMX_SC_R_VPU>, <&pd IMX_SC_R_VPU_MU_1>, <&pd IMX_SC_R_VPU_MU_2>;
-       power-domain-names = "vpuenc1", "vpuenc2", "vpu", "vpumu1", "vpumu2";
+                       <&pd IMX_SC_R_VPU>;
+       power-domain-names = "vpuenc1", "vpuenc2", "vpu";
+       mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx",
+                    "enc2_tx0", "enc2_tx1", "enc2_rx";
+       mboxes = <&mu1_m0 0 0
+                 &mu1_m0 0 1
+                 &mu1_m0 1 0
+                 &mu2_m0 0 0
+                 &mu2_m0 0 1
+                 &mu2_m0 1 0>;
        status = "okay";
 
        core0@1020000 {

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 4d7ccf6..0119a4c 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -802,6 +802,10 @@
        reg-rpc-system = <0x40000000>;
        resolution-max = <1920 1080>;
        fps-max = <120>;
+       mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx";
+       mboxes = <&mu1_m0 0 0
+                 &mu1_m0 0 1
+                 &mu1_m0 1 0>;
        status = "okay";
 
        core0@1020000 {