/**
* struct mt7621_pcie - PCIe host information
* @base: IO Mapped Register Base
- * @sysctl: system control mapped register base
* @io: IO resource
* @mem: non-prefetchable memory resource
* @busn: bus range
*/
struct mt7621_pcie {
void __iomem *base;
- void __iomem *sysctl;
struct device *dev;
struct resource io;
struct resource mem;
static void mt7621_enable_phy(struct mt7621_pcie_port *port)
{
- struct mt7621_pcie *pcie = port->pcie;
- u32 chip_rev_id = ioread32(pcie->sysctl + MT7621_CHIP_REV_ID);
+ u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2)
bypass_pipe_rst(port);
if (IS_ERR(pcie->base))
return PTR_ERR(pcie->base);
- err = of_address_to_resource(node, 4, ®s);
- if (err) {
- dev_err(dev, "missing \"reg\" property\n");
- return err;
- }
-
- pcie->sysctl = devm_ioremap_resource(dev, ®s);
- if (IS_ERR(pcie->sysctl))
- return PTR_ERR(pcie->sysctl);
-
for_each_available_child_of_node(node, child) {
int slot;