MLK-12796-02 ARM: dts: imx: Add additional pinfunc define for imx6ull

On i.MX6ULL, the pin MUX and CTRL register of BOOT_MODEx and TAMPERx
pins have been move to the IOMUXC_SNVS. Add additional pinfunc define
and correct the pinctrl binding.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-cs42888.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-cs42888.dts
index 86699fe..2d90d0a 100644 (file)
--- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-cs42888.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-cs42888.dts
@@ -135,7 +135,7 @@
 
 &sai2 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_sai2>;
+       pinctrl-0 = <&pinctrl_sai2 &pinctrl_sai2_hp_det_b>;
        assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
                        <&clks IMX6UL_CLK_SAI2>;
        assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;

diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-wm8958.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-wm8958.dts
index 0e55c83..fbbc648 100644 (file)
--- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-wm8958.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-wm8958.dts
@@ -102,7 +102,7 @@
 
 &sai2 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_sai2>;
+       pinctrl-0 = <&pinctrl_sai2 &pinctrl_sai2_hp_det_b>;
        assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
                        <&clks IMX6UL_CLK_SAI2>;
        assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;

diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts
index 6735ca6..136cba0 100644 (file)
--- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts
@@ -402,13 +402,6 @@
                        >;
                };
 
-               pinctrl_bt: btgrp {
-                       fsl,pins = <
-                               MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x80000000
-                               MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x80000000
-                               MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x80000000
-                       >;
-               };
 
                pinctrl_csi1: csi1grp {
                        fsl,pins = <
@@ -656,7 +649,6 @@
                                MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA     0x110b0
                                MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA     0x1f0b8
                                MX6UL_PAD_SD1_CLK__SAI2_MCLK          0x1b0b0
-                               MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00   0x17059
                        >;
                };
 
@@ -852,6 +844,24 @@
        };
 };
 
+&iomuxc_snvs {
+       imx6ul-ddr3-arm2 {
+               pinctrl_bt: btgrp {
+                       fsl,pins = <
+                               MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06     0x80000000
+                               MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09     0x80000000
+                               MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05     0x80000000
+                       >;
+               };
+
+               pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
+                       fsl,pins = <
+                               MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00   0x17059
+                       >;
+               };
+       };
+};
+
 &lcdif {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_lcdif_dat

diff --git a/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h
new file mode 100644 (file)
index 0000000..da3f412
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H
+#define __DTS_IMX6ULL_PINFUNC_SNVS_H
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10                          0x0000 0x0044 0x0000 0x5 0x0
+#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11                          0x0004 0x0048 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00                        0x0008 0x004C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01                        0x000C 0x0050 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02                        0x0010 0x0054 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03                        0x0014 0x0058 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04                        0x0018 0x005C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05                        0x001C 0x0060 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06                        0x0020 0x0064 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07                        0x0024 0x0068 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08                        0x0028 0x006C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09                        0x002C 0x0070 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */
+

diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 8462d6b..3b1bc83 100644 (file)
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "imx6ull-pinfunc.h"
+#include "imx6ull-pinfunc-snvs.h"
 #include "skeleton.dtsi"
 
 / {
@@ -1145,7 +1146,16 @@
                                /* epdc-ram = <&gpr 0x4 30>; */
                                status = "disabled";
                        };
-                       /* SNVS_GPR and IOMUXC_SNVS not added */
+
+                       iomuxc_snvs: iomuxc-snvs@02290000 {
+                               compatible = "fsl,imx6ull-iomuxc-snvs";
+                               reg = <0x02290000 0x10000>;
+                       };
+
+                       snvs_gpr: snvs-gpr@0x02294000 {
+                               compatible = "fsl, imx6ull-snvs-gpr";
+                               reg = <0x02294000 0x10000>;
+                       };
                };
        };
 };