MLK-15046 arm64: dts: fsl-imx8qxp: change CAN1 & 2 to use CAN0 clk and power domain

Per information from Ranjani:
"Looks like all three CANs are controlled by one DSC clock slice
(SLSLICE[4]). Currently the SCFW is only allocating this clock to CAN0,
which explains why CAN0 works.  And once CAN0 is enabled, CAN1 and CAN2
access will also work."

This is a workaround patch to make CAN1 & CAN2 work temporarily.
Once SCFW supports shared clock management for all CAN, we can revert
this patch.

Cc: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index 64ce351..00477b5 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -814,12 +814,13 @@
                compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
                reg = <0x0 0x5a8e0000 0x0 0x10000>;
                interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk IMX8QXP_CAN1_IPG_CLK>,
-                        <&clk IMX8QXP_CAN1_CLK>;
+               /* CAN0 clock and PD is shared among all CAN instances */
+               clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
+                        <&clk IMX8QXP_CAN0_CLK>;
                clock-names = "ipg", "per";
-               assigned-clocks = <&clk IMX8QXP_CAN1_CLK>;
+               assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
                assigned-clock-rates = <24000000>;
-               power-domains = <&pd_dma_flexcan1>;
+               power-domains = <&pd_dma_flexcan0>;
                status = "disabled";
        };
 
@@ -827,12 +828,13 @@
                compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
                reg = <0x0 0x5a8f0000 0x0 0x10000>;
                interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk IMX8QXP_CAN2_IPG_CLK>,
-                        <&clk IMX8QXP_CAN2_CLK>;
+               /* CAN0 clock and PD is shared among all CAN instances */
+               clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
+                        <&clk IMX8QXP_CAN0_CLK>;
                clock-names = "ipg", "per";
-               assigned-clocks = <&clk IMX8QXP_CAN2_CLK>;
+               assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
                assigned-clock-rates = <24000000>;
-               power-domains = <&pd_dma_flexcan2>;
+               power-domains = <&pd_dma_flexcan0>;
                status = "disabled";
        };