PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM

The PCIE_AXI_WINDOW0 register defines the inbound window size for
requests coming from PCI endpoints. Requests outside of this window will
be treated as unsupported requests.

Enlarge this window size from 2^31 to 2^33 to support a 8GB address
space (which gives endpoints DMA access to full 4GB DRAM address range
- physical DRAM starts at 0x40000000).

Reported-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index c42fe5c..0b6c728 100644 (file)
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -90,6 +90,12 @@
 #define AHB2PCIE_SIZE(x)       ((x) & GENMASK(4, 0))
 #define PCIE_AXI_WINDOW0       0x448
 #define WIN_ENABLE             BIT(7)
+/*
+ * Define PCIe to AHB window size as 2^33 to support max 8GB address space
+ * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
+ * start from 0x40000000).
+ */
+#define PCIE2AHB_SIZE  0x21
 
 /* PCIe V2 configuration transaction header */
 #define PCIE_CFG_HEADER0       0x460
@@ -713,7 +719,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
        writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
 
        /* Set PCIe to AXI translation memory space.*/
-       val = fls(0xffffffff) | WIN_ENABLE;
+       val = PCIE2AHB_SIZE | WIN_ENABLE;
        writel(val, port->base + PCIE_AXI_WINDOW0);
 
        return 0;