arm64: dts: imx8qm: Add LPDDR4 validation board single cluster support
authorAnson Huang <Anson.Huang@nxp.com>
Wed, 6 Nov 2019 02:33:51 +0000 (10:33 +0800)
committerDong Aisheng <aisheng.dong@nxp.com>
Mon, 14 Dec 2020 03:20:36 +0000 (11:20 +0800)
Add *-ca53.dtb and *-ca72.dtb to support booting up single
cluster on LPDDR4 validation board, to boot up single A72 cluster,
dedicated flash.bin needs to be used.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
arch/arm64/boot/dts/freescale/Makefile
arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts [new file with mode: 0644]
arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts [new file with mode: 0644]

index ab0d468..edec94f 100644 (file)
@@ -56,7 +56,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \
                          imx8qm-mek-hdmi.dtb imx8qm-mek-dsp.dtb \
                          imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \
                          imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \
-                         imx8qm-mek-ca72.dtb
+                         imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \
+                         imx8qm-lpddr4-val-ca72.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8dxl-phantom-mek.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts
new file mode 100644 (file)
index 0000000..53f8bad
--- /dev/null
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qm-lpddr4-val.dts"
+
+&thermal_zones {
+       /delete-node/   cpu-thermal1;
+
+       pmic-thermal0 {
+               cooling-maps {
+                       map0 {
+                               cooling-device =
+                               <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                               <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                               <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                               <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                       };
+               };
+       };
+};
+
+&cpus {
+       /delete-node/ cpu-map;
+       /delete-node/ cpu@100;
+       /delete-node/ cpu@101;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts
new file mode 100644 (file)
index 0000000..e59fd9c
--- /dev/null
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qm-lpddr4-val.dts"
+
+&thermal_zones {
+       /delete-node/ cpu-thermal0;
+
+       pmic-thermal0 {
+               cooling-maps {
+                       map0 {
+                               cooling-device =
+                               <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                               <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                       };
+               };
+       };
+};
+
+&cpus {
+       /delete-node/ cpu-map;
+       /delete-node/ cpu@0;
+       /delete-node/ cpu@1;
+       /delete-node/ cpu@2;
+       /delete-node/ cpu@3;
+};