Add *-ca53.dtb and *-ca72.dtb to support booting up single
cluster on LPDDR4 validation board, to boot up single A72 cluster,
dedicated flash.bin needs to be used.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
imx8qm-mek-hdmi.dtb imx8qm-mek-dsp.dtb \
imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \
imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \
- imx8qm-mek-ca72.dtb
+ imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \
+ imx8qm-lpddr4-val-ca72.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-phantom-mek.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qm-lpddr4-val.dts"
+
+&thermal_zones {
+ /delete-node/ cpu-thermal1;
+
+ pmic-thermal0 {
+ cooling-maps {
+ map0 {
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ /delete-node/ cpu@101;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qm-lpddr4-val.dts"
+
+&thermal_zones {
+ /delete-node/ cpu-thermal0;
+
+ pmic-thermal0 {
+ cooling-maps {
+ map0 {
+ cooling-device =
+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@0;
+ /delete-node/ cpu@1;
+ /delete-node/ cpu@2;
+ /delete-node/ cpu@3;
+};