MLK-17689-3: arm64: dts: fsl-imx8mq-evk: Fix clocks for DCSS-RM67191

Currently, the default clock configuration for DCSS configures the pixel
clock to be sourced from VIDEO_PLL2, but this source cannot be used by the
DSI PHY_REF clock.
So, in order to make DCSS working with DSI, we need to have them both
(DCSS and DSI PHY) use the same clock source: VIDEO_PLL1.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts
index c537a03..081fd8e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts
@@ -22,21 +22,29 @@
        status = "okay";
        disp-dev = "mipi_disp";
 
-       assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
+       clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+                <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+                <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+                <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
+                <&clk IMX8MQ_CLK_DUMMY>,
+                <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
+       clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
+
+       assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
+                         <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
                          <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
                          <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
-                         <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
                          <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
                          <&clk IMX8MQ_VIDEO_PLL1>;
-       assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+       assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+                                <&clk IMX8MQ_SYS1_PLL_800M>,
                                 <&clk IMX8MQ_SYS1_PLL_800M>,
-                                <&clk IMX8MQ_CLK_DISP_RTRM_CG>,
                                 <&clk IMX8MQ_VIDEO_PLL1_OUT>,
                                 <&clk IMX8MQ_CLK_25M>;
-       assigned-clock-rates = <800000000>,
+       assigned-clock-rates = <600000000>,
+                              <800000000>,
                               <400000000>,
                               <400000000>,
-                              <120000000>,
                               <0>,
                               <599999999>;