MLK-25441 clk: imx8mp: fix ISP clocks in mediamix

ISP1/2 share the core/axi/ahb clock in mediamix
BIT13/14/15(ISP1_core/axi/ahb) should be reserved bits.

The patch fixed it.

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: G.n. Zhou <guoniu.zhou@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 0d72ea9..3bf51db 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1503,9 +1503,9 @@
                                        compatible = "fsl,imx8mp-isp";
                                        reg = <0x32e10000 0x10000>;
                                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                                       clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_COR>,
-                                                <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AXI>,
-                                                <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AHB>;
+                                       clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_COR>,
+                                                <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AXI>,
+                                                <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AHB>;
                                        clock-names = "core", "axi", "ahb";
                                        assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
                                        assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
@@ -1521,9 +1521,9 @@
                                        compatible = "fsl,imx8mp-isp";
                                        reg = <0x32e20000 0x10000>;
                                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                                       clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_COR>,
-                                                <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AXI>,
-                                                <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AHB>;
+                                       clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_COR>,
+                                                <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AXI>,
+                                                <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AHB>;
                                        clock-names = "core", "axi", "ahb";
                                        assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
                                        assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 56d85b8..7e334dc 100644 (file)
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -148,12 +148,9 @@ static struct imx_blk_ctrl_hw imx8mp_media_blk_ctrl_hws[] = {
        IMX_BLK_CTRL_CLK_GATE("mipi_csi2_aclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_ACLK, 0x4, 10, "media_cam2_pix_root_clk"),
        IMX_BLK_CTRL_CLK_GATE("lcdif2_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_PIXEL, 0x4, 11, "media_disp2_pix_root_clk"),
        IMX_BLK_CTRL_CLK_GATE("lcdif2_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_APB, 0x4, 12, "media_apb_root_clk"),
-       IMX_BLK_CTRL_CLK_GATE("isp1_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_COR, 0x4, 13, "media_isp_root_clk"),
-       IMX_BLK_CTRL_CLK_GATE("isp1_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AXI, 0x4, 14, "media_axi_root_clk"),
-       IMX_BLK_CTRL_CLK_GATE("isp1_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AHB, 0x4, 15, "media_apb_root_clk"),
-       IMX_BLK_CTRL_CLK_GATE("isp0_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_COR, 0x4, 16, "media_isp_root_clk"),
-       IMX_BLK_CTRL_CLK_GATE("isp0_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AXI, 0x4, 17, "media_axi_root_clk"),
-       IMX_BLK_CTRL_CLK_GATE("isp0_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AHB, 0x4, 18, "media_apb_root_clk"),
+       IMX_BLK_CTRL_CLK_GATE("isp_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_COR, 0x4, 16, "media_isp_root_clk"),
+       IMX_BLK_CTRL_CLK_GATE("isp_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AXI, 0x4, 17, "media_axi_root_clk"),
+       IMX_BLK_CTRL_CLK_GATE("isp_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AHB, 0x4, 18, "media_apb_root_clk"),
        IMX_BLK_CTRL_CLK_GATE("dwe_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_COR, 0x4, 19, "media_axi_root_clk"),
        IMX_BLK_CTRL_CLK_GATE("dwe_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AXI, 0x4, 20, "media_axi_root_clk"),
        IMX_BLK_CTRL_CLK_GATE("dwe_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AHB, 0x4, 21, "media_apb_root_clk"),

diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 2e54f13..ecd81c4 100644 (file)
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -457,12 +457,9 @@
 #define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_ACLK       10
 #define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_PIXEL         11
 #define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_APB           12
-#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_COR             13
-#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AXI             14
-#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AHB             15
-#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_COR             16
-#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AXI             17
-#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AHB             18
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_COR              16
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AXI              17
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AHB              18
 #define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_COR              19
 #define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AXI              20
 #define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AHB              21