MLK-16748-03: dts: Add fsl-imx8mq-evk-drm.dts for drm driver

Enable DCSS DRM and HDMI DRM driver.
Disable DCSS Framebuffer and HDMI Framebuffer driver.

Set IMX8MQ_CLK_DISP_APB_SRC source from IMX8MQ_SYS2_PLL_125M temporary,
will be set back to IMX8MQ_SYS1_PLL_800M
after DCSS APB clock affect HDMI Core clock issue resolved on B0 SOC.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index c57d682..dc8bd01 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \
 dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-evk.dtb \
                                 fsl-imx8mq-evk-od.dtb \
                                 fsl-imx8mq-evk-4k.dtb \
+                                fsl-imx8mq-evk-drm.dtb \
                                 fsl-imx8mq-evk-lcdif-dsi.dtb \
                                 fsl-imx8mq-evk-m4.dtb \
                                 fsl-imx8mq-evk-pcie1-m2.dtb

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-drm.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-drm.dts
new file mode 100644 (file)
index 0000000..3d4919b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-drm.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8mq-evk.dts"
+
+/ {
+       dcss_drm: dcss@0x32e00000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "nxp,imx8mq-dcss";
+               reg = <0x0 0x32e00000 0x0 0x30000>;
+               interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>, <5 IRQ_TYPE_LEVEL_HIGH>,
+                                    <6 IRQ_TYPE_LEVEL_HIGH>, <8 IRQ_TYPE_EDGE_RISING>;
+               interrupt-names = "dpr_dc_ch0", "dpr_dc_ch1", "dpr_dc_ch2", "ctx_ld",
+                                                 "dtg_prg1";
+               interrupt-parent = <&irqsteer_dcss>;
+               clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+                        <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+                        <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+                        <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
+                        <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
+               clock-names = "apb", "axi", "rtrm", "pixel", "dtrc";
+               assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
+                                 <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
+                                 <&clk IMX8MQ_CLK_DISP_APB_SRC>,
+                                 <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
+                                 <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>;
+               assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+                                        <&clk IMX8MQ_SYS1_PLL_800M>,
+                                        <&clk IMX8MQ_SYS2_PLL_125M>,
+                                        <&clk IMX8MQ_SYS1_PLL_800M>;
+               assigned-clock-rates = <594000000>,
+                                      <800000000>,
+                                      <125000000>,
+                                      <400000000>,
+                                      <400000000>;
+
+               disp-dev = "hdmi_disp";
+
+               status = "okay";
+
+               dcss_disp0: port@0 {
+                       reg = <0>;
+
+                       dcss_disp0_hdmi: hdmi-endpoint {
+                               remote-endpoint = <&hdmi_disp>;
+                       };
+               };
+       };
+
+       display-subsystem {
+               compatible = "fsl,imx-display-subsystem";
+               ports = <&dcss_disp0>;
+       };
+
+       hdmi_drm: hdmi_drm@32c00000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "fsl,imx8mq-hdmi";
+               reg = <0x0 0x32c00000 0x0 0x100000>,    /* HDP registers */
+                               <0x0 0x32e40000 0x0 0x40000>;   /* HDP SEC register */
+               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&disp_pd>;
+               port@0 {
+                       reg = <0>;
+                               hdmi_disp: endpoint {
+                               remote-endpoint = <&dcss_disp0_hdmi>;
+                       };
+               };
+       };
+};
+
+&dcss {
+       status = "disabled";
+};
+
+&hdmi {
+       status = "disabled";
+};