memory@40000000 {
device_type = "memory";
- reg = <0x0 0x40000000 0 0xc0000000>,
- <0x1 0x00000000 0 0xc0000000>;
+ reg = <0x0 0x40000000 0 0x80000000>;
};
reg_can1_stby: regulator-can1-stby {
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN SZ_32M
-/* Totally 6GB DDR */
+/* Totally 2GB DDR */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
-#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
-#define PHYS_SDRAM_2 0x100000000
-#ifdef CONFIG_TARGET_IMX8MP_DDR4_SOMDEVICES
-#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
-#else
-#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
-#endif
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR