The MIB RAM and FIFO receive start register does not exist on
i.MX6ULL. Accessing these register will cause enet not work well or
cause system report fault.
Reported-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit
5fb09cab9bb3cc4cef02239299d02cec666396ab)
writel(0x00000000, &fec->eth->gaddr2);
/* Do not access reserved register for i.MX6UL */
- if (!is_mx6ul()) {
+ if (!is_mx6ul() && !is_mx6ull()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);