ipu_common: Let the MX6 IPU clock be calculated in run-time
authorFabio Estevam <fabio.estevam@nxp.com>
Wed, 6 Sep 2017 16:49:31 +0000 (13:49 -0300)
committerAnatolij Gustschin <agust@denx.de>
Mon, 11 Sep 2017 10:46:51 +0000 (12:46 +0200)
MX6Q/QP IPU operates at 264MHz and MX6DL IPU at 198MHz.

When running a SPL target, which supports multiple MX6 variants we cannot
properly setup the IPU clock frequency via CONFIG_IPUV3_CLK option as
such decision is done in build-time currently.

Remove the CONFIG_IPUV3_CLK option and let the IPU clock frequency be
configured in run-time on mx6.

Reported-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
[agust: fixed #endif in cgtqmx6eval.h]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
22 files changed:
drivers/video/ipu_common.c
include/configs/advantech_dms-ba16.h
include/configs/apalis_imx6.h
include/configs/aristainetos-common.h
include/configs/cgtqmx6eval.h
include/configs/cm_fx6.h
include/configs/colibri_imx6.h
include/configs/embestmx6boards.h
include/configs/ge_bx50v3.h
include/configs/gw_ventana.h
include/configs/imx6-engicam.h
include/configs/m53evk.h
include/configs/mx51evk.h
include/configs/mx53cx9020.h
include/configs/mx53loco.h
include/configs/mx6cuboxi.h
include/configs/mx6sabre_common.h
include/configs/nitrogen6x.h
include/configs/novena.h
include/configs/tbs2910.h
include/configs/wandboard.h
scripts/config_whitelist.txt

index f259fb9..96229da 100644 (file)
@@ -19,6 +19,7 @@
 #include <linux/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
 #include <div64.h>
 #include "ipu.h"
 #include "ipu_regs.h"
@@ -81,6 +82,11 @@ struct ipu_ch_param {
 
 #define IPU_SW_RST_TOUT_USEC   (10000)
 
+#define IPUV3_CLK_MX51         133000000
+#define IPUV3_CLK_MX53         200000000
+#define IPUV3_CLK_MX6Q         264000000
+#define IPUV3_CLK_MX6DL                198000000
+
 void clk_enable(struct clk *clk)
 {
        if (clk) {
@@ -196,7 +202,6 @@ static void clk_ipu_disable(struct clk *clk)
 
 static struct clk ipu_clk = {
        .name = "ipu_clk",
-       .rate = CONFIG_IPUV3_CLK,
 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        .enable_reg = (u32 *)(CCM_BASE_ADDR +
                offsetof(struct mxc_ccm_reg, CCGR5)),
@@ -476,6 +481,13 @@ int ipu_probe(void)
        g_pixel_clk[1] = &pixel_clk[1];
 
        g_ipu_clk = &ipu_clk;
+#if defined(CONFIG_MX51)
+       g_ipu_clk->rate = IPUV3_CLK_MX51;
+#elif defined(CONFIG_MX53)
+       g_ipu_clk->rate = IPUV3_CLK_MX53;
+#else
+       g_ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q;
+#endif
        debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
        g_ldb_clk = &ldb_clk;
        debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
index 86302cf..09f470c 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK                260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #endif
index a15f19d..9022a9d 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK               260000000
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
index d24d564..397afbb 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 198000000
 #define CONFIG_IMX_VIDEO_SKIP
 
 #define CONFIG_PWM_IMX
index 8f7f26b..2e8993d 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#ifdef CONFIG_MX6DL
-#define CONFIG_IPUV3_CLK 198000000
-#else
-#define CONFIG_IPUV3_CLK 264000000
-#endif
 #define CONFIG_IMX_HDMI
 
 /* SATA */
index 2d6132d..e278961 100644 (file)
 
 /* Display */
 #define CONFIG_VIDEO_IPUV3
-#define CONFIG_IPUV3_CLK          260000000
 #define CONFIG_IMX_HDMI
 
 #define CONFIG_SPLASH_SCREEN
index db71369..5fd9aab 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK               260000000
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
index 2456230..3f128e6 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
index 45f845b..a0468d2 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #endif
index 9c26059..128a6e5 100644 (file)
 /* Framebuffer and LCD */
 #define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK          260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #define CONFIG_VIDEO_BMP_LOGO
index a1b7036..c34dc30 100644 (file)
 
 /* Framebuffer */
 #ifdef CONFIG_VIDEO_IPUV3
-# define CONFIG_IPUV3_CLK              260000000
 # define CONFIG_IMX_VIDEO_SKIP
 
 # define CONFIG_SPLASH_SCREEN
index 74b627c..dcc12dd 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-#define CONFIG_IPUV3_CLK               200000000
 #endif
 
 /*
index c89cb0f..3ecb92c 100644 (file)
@@ -84,7 +84,6 @@
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK       133000000
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
index d78a877..ccb1a4a 100644 (file)
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK       200000000
 
 #endif /* __CONFIG_H */
index 45b9bbf..e973b35 100644 (file)
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK       200000000
 
 #endif                         /* __CONFIG_H */
index a168577..4e12de1 100644 (file)
@@ -41,7 +41,6 @@
 
 /* Framebuffer */
 #define CONFIG_VIDEO_IPUV3
-#define CONFIG_IPUV3_CLK               260000000
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
index 036c76d..f083dc8 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#ifdef CONFIG_MX6DL
-#define CONFIG_IPUV3_CLK 198000000
-#else
-#define CONFIG_IPUV3_CLK 264000000
-#endif
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
index d32d8f8..520a52c 100644 (file)
@@ -80,7 +80,6 @@
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024)
 #define CONFIG_BMP_16BPP
-#define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
index be8c691..4480aaf 100644 (file)
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK               260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #endif
index f98bf95..849d4a6 100644 (file)
@@ -64,7 +64,6 @@
 /* Framebuffer */
 #ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_IPUV3
-#define CONFIG_IPUV3_CLK               260000000
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
index d9237d7..3ba4c29 100644 (file)
@@ -71,7 +71,6 @@
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #endif
index 9ce0c3f..4a0eae3 100644 (file)
@@ -1119,7 +1119,6 @@ CONFIG_IPAM390_GPIO_BOOTMODE
 CONFIG_IPAM390_GPIO_LED_GREEN
 CONFIG_IPAM390_GPIO_LED_RED
 CONFIG_IPROC
-CONFIG_IPUV3_CLK
 CONFIG_IP_DEFRAG
 CONFIG_IRAM_BASE
 CONFIG_IRAM_END