bool
select PM_GENERIC_DOMAINS if PM
+config HAVE_IMX_GPCV2
+ bool
+ select PM_GENERIC_DOMAINS if PM
+
config HAVE_IMX_MMDC
bool
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select MFD_SYSCON
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if SMP
select PL310_ERRATA_769419 if CACHE_L2X0
config SOC_IMX6Q
select ARM_ERRATA_764369 if SMP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD
+ select PCI_DOMAINS if PCI
select PINCTRL_IMX6Q
select SOC_IMX6
+ select MXC_MLB150
help
This enables support for Freescale i.MX6 Quad processor.
select SOC_IMX6
select HAVE_IMX_RPMSG
select RPMSG
+ select IMX_SEMA4
+ select MXC_MLB150
+ select KEYBOARD_SNVS_PWRKEY
help
This enables support for Freescale i.MX6 SoloX processor.
bool "i.MX6 UltraLite support"
select PINCTRL_IMX6UL
select SOC_IMX6
+ select KEYBOARD_SNVS_PWRKEY
help
This enables support for Freescale i.MX6 UltraLite processor.
select HAVE_IMX_SRC
select HAVE_IMX_RPMSG
select RPMSG
+ select KEYBOARD_SNVS_PWRKEY
+ select HAVE_IMX_GPCV2
+ select CPU_V7
help
This enables support for Freescale i.MX7 Dual processor.
-obj-y := cpu.o system.o irq-common.o
+obj-y := cpu.o system.o irq-common.o common.o
obj-$(CONFIG_SOC_IMX21) += mm-imx21.o
obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
-obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o gpcv2.o
+obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
+obj-$(CONFIG_HAVE_IMX_GPCV2) += gpcv2.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_DDRC) += ddrc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
obj-$(CONFIG_HAVE_IMX_RPMSG) += imx_rpmsg.o
-ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7)$(CONFIG_SOC_LS1021A),)
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
endif
+obj-y += busfreq_lpddr2.o busfreq-imx.o busfreq_ddr3.o
AFLAGS_ddr3_freq_imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o ddr3_freq_imx6.o
AFLAGS_lpddr2_freq_imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o lpddr2_freq_imx6.o
AFLAGS_ddr3_freq_imx6sx.o :=-Wa,-march=armv7-a
AFLAGS_lpddr2_freq_imx6sx.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o ddr3_freq_imx6sx.o lpddr2_freq_imx6sx.o busfreq_lpddr2.o
-obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
+obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o ddr3_freq_imx6sx.o \
+ lpddr2_freq_imx6sx.o mu.o
+obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o ddr3_freq_imx6sx.o \
+ lpddr2_freq_imx6sx.o
obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o mu.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_smp_wfe.o :=-Wa,-march=armv7-a
AFLAGS_ddr3_freq_imx7d.o :=-Wa,-march=armv7-a
AFLAGS_lpddr3_freq_imx.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_SOC_IMX7D) += pm-imx7.o busfreq-imx.o busfreq_ddr3.o ddr3_freq_imx7d.o smp_wfe.o lpddr3_freq_imx.o
+obj-$(CONFIG_SOC_IMX7D) += pm-imx7.o ddr3_freq_imx7d.o smp_wfe.o \
+ lpddr3_freq_imx.o
obj-$(CONFIG_SOC_IMX1) += mach-imx1.o
obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_net.h>
+#include <linux/slab.h>
+
+unsigned long iram_tlb_base_addr;
+unsigned long iram_tlb_phys_addr;
+
+unsigned long save_ttbr1(void)
+{
+ unsigned long lttbr1;
+ asm volatile(
+ ".align 4\n"
+ "mrc p15, 0, %0, c2, c0, 1\n"
+ : "=r" (lttbr1)
+ );
+ return lttbr1;
+}
+
+void restore_ttbr1(unsigned long ttbr1)
+{
+ asm volatile(
+ ".align 4\n"
+ "mcr p15, 0, %0, c2, c0, 1\n"
+ : : "r" (ttbr1)
+ );
+}
+
+#define OCOTP_MACn(n) (0x00000620 + (n) * 0x10)
+void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat)
+{
+ struct device_node *ocotp_np, *enet_np, *from = NULL;
+ void __iomem *base;
+ struct property *newmac;
+ u32 macaddr_low;
+ u32 macaddr_high = 0;
+ u32 macaddr1_high = 0;
+ u8 *macaddr;
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ enet_np = of_find_compatible_node(from, NULL, enet_compat);
+ if (!enet_np)
+ return;
+
+ from = enet_np;
+
+ if (of_get_mac_address(enet_np))
+ goto put_enet_node;
+
+ ocotp_np = of_find_compatible_node(NULL, NULL, ocotp_compat);
+ if (!ocotp_np) {
+ pr_warn("failed to find ocotp node\n");
+ goto put_enet_node;
+ }
+
+ base = of_iomap(ocotp_np, 0);
+ if (!base) {
+ pr_warn("failed to map ocotp\n");
+ goto put_ocotp_node;
+ }
+
+ macaddr_low = readl_relaxed(base + OCOTP_MACn(1));
+ if (i)
+ macaddr1_high = readl_relaxed(base + OCOTP_MACn(2));
+ else
+ macaddr_high = readl_relaxed(base + OCOTP_MACn(0));
+
+ newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
+ if (!newmac)
+ goto put_ocotp_node;
+
+ newmac->value = newmac + 1;
+ newmac->length = 6;
+ newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
+ if (!newmac->name) {
+ kfree(newmac);
+ goto put_ocotp_node;
+ }
+
+ macaddr = newmac->value;
+ if (i) {
+ macaddr[5] = (macaddr_low >> 16) & 0xff;
+ macaddr[4] = (macaddr_low >> 24) & 0xff;
+ macaddr[3] = macaddr1_high & 0xff;
+ macaddr[2] = (macaddr1_high >> 8) & 0xff;
+ macaddr[1] = (macaddr1_high >> 16) & 0xff;
+ macaddr[0] = (macaddr1_high >> 24) & 0xff;
+ } else {
+ macaddr[5] = macaddr_high & 0xff;
+ macaddr[4] = (macaddr_high >> 8) & 0xff;
+ macaddr[3] = (macaddr_high >> 16) & 0xff;
+ macaddr[2] = (macaddr_high >> 24) & 0xff;
+ macaddr[1] = macaddr_low & 0xff;
+ macaddr[0] = (macaddr_low >> 8) & 0xff;
+ }
+
+ of_update_property(enet_np, newmac);
+
+put_ocotp_node:
+ of_node_put(ocotp_np);
+put_enet_node:
+ of_node_put(enet_np);
+ }
+}
+
+#ifndef CONFIG_HAVE_IMX_GPC
+int imx_gpc_mf_request_on(unsigned int irq, unsigned int on) { return 0; }
+EXPORT_SYMBOL_GPL(imx_gpc_mf_request_on);
+#endif
+
+#if !defined(CONFIG_SOC_IMX6SL)
+u32 imx6_lpddr2_freq_change_start, imx6_lpddr2_freq_change_end;
+void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode) {}
+#endif
+
+#if !defined(CONFIG_SOC_IMX6SX) && !defined(CONFIG_SOC_IMX6UL)
+u32 imx6_up_ddr3_freq_change_start, imx6_up_ddr3_freq_change_end;
+struct imx6_busfreq_info {
+} __aligned(8);
+void imx6_up_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info) {}
+void imx6_up_lpddr2_freq_change(u32 freq, int bus_freq_mode) {}
+#endif
+
+#if !defined(CONFIG_SOC_IMX6Q)
+u32 mx6_ddr3_freq_change_start, mx6_ddr3_freq_change_end;
+u32 wfe_ddr3_freq_change_start, wfe_ddr3_freq_change_end;
+void mx6_ddr3_freq_change(u32 freq, void *ddr_settings,
+ bool dll_mode, void *iomux_offsets) {}
+void wfe_ddr3_freq_change(u32 cpuid, u32 *ddr_freq_change_done) {}
+#endif
+
+#if !defined(CONFIG_SOC_IMX7D)
+void imx7_smp_wfe(u32 cpuid, u32 ocram_base) {}
+void imx7d_ddr3_freq_change(u32 freq) {}
+#endif
+
unsigned int imx_gpc_is_mf_mix_off(void);
void imx6sx_set_m4_highfreq(bool high_freq);
void imx_mu_enable_m4_irqs_in_gic(bool enable);
+#ifdef CONFIG_HAVE_IMX_GPC
void imx_gpc_add_m4_wake_up_irq(u32 irq, bool enable);
+unsigned int imx_gpc_is_m4_sleeping(void);
+#else
+static inline void imx_gpc_add_m4_wake_up_irq(u32 irq, bool enable) {}
+static inline unsigned int imx_gpc_is_m4_sleeping(void) { return 0; }
+#endif
void imx_gpc_hold_m4_in_sleep(void);
void imx_gpc_release_m4_in_sleep(void);
void mcc_receive_from_mu_buffer(unsigned int index, unsigned int *data);
void mcc_send_via_mu_buffer(unsigned int index, unsigned int data);
-unsigned int imx_gpc_is_m4_sleeping(void);
bool imx_mu_is_m4_in_low_freq(void);
enum mxc_cpu_pwr_mode {
unsigned int imx_gpc_is_mf_mix_off(void);
void imx_gpcv2_pre_suspend(bool arm_power_off);
void imx_gpcv2_post_resume(void);
-void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn);
unsigned int imx_gpcv2_is_mf_mix_off(void);
int imx_gpc_mf_power_on(unsigned int irq, unsigned int on);
+#ifdef CONFIG_HAVE_IMX_GPCV2
int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on);
+void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn);
+#else
+static inline int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on) { return 0; }
+static inline void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) {}
+#endif
void __init imx_gpcv2_check_dt(void);
void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode);
void imx_gpcv2_set_cpu_power_gate_in_idle(bool pdn);
+unsigned long save_ttbr1(void);
+void restore_ttbr1(unsigned long ttbr1);
void imx_gpc_mask_all(void);
void imx_gpc_restore_all(void);
void imx_gpc_hwirq_mask(unsigned int hwirq);
void imx6_set_int_mem_clk_lpm(bool enable);
void imx6sl_set_wait_clk(bool enter);
void imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat);
+#ifdef CONFIG_HAVE_IMX_MMDC
int imx_mmdc_get_ddr_type(void);
+#else
+static inline int imx_mmdc_get_ddr_type(void) { return 0; }
+#endif
+#ifdef CONFIG_HAVE_DDRC
int imx_ddrc_get_ddr_type(void);
+#else
+static inline int imx_ddrc_get_ddr_type(void) { return 0; }
+#endif
void imx_cpu_die(unsigned int cpu);
int imx_cpu_kill(unsigned int cpu);
void imx_busfreq_map_io(void);
pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
}
-#define OCOTP_MACn(n) (0x00000620 + (n) * 0x10)
-void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat)
-{
- struct device_node *ocotp_np, *enet_np, *from = NULL;
- void __iomem *base;
- struct property *newmac;
- u32 macaddr_low;
- u32 macaddr_high = 0;
- u32 macaddr1_high = 0;
- u8 *macaddr;
- int i;
-
- for (i = 0; i < 2; i++) {
- enet_np = of_find_compatible_node(from, NULL, enet_compat);
- if (!enet_np)
- return;
-
- from = enet_np;
-
- if (of_get_mac_address(enet_np))
- goto put_enet_node;
-
- ocotp_np = of_find_compatible_node(NULL, NULL, ocotp_compat);
- if (!ocotp_np) {
- pr_warn("failed to find ocotp node\n");
- goto put_enet_node;
- }
-
- base = of_iomap(ocotp_np, 0);
- if (!base) {
- pr_warn("failed to map ocotp\n");
- goto put_ocotp_node;
- }
-
- macaddr_low = readl_relaxed(base + OCOTP_MACn(1));
- if (i)
- macaddr1_high = readl_relaxed(base + OCOTP_MACn(2));
- else
- macaddr_high = readl_relaxed(base + OCOTP_MACn(0));
-
- newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
- if (!newmac)
- goto put_ocotp_node;
-
- newmac->value = newmac + 1;
- newmac->length = 6;
- newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
- if (!newmac->name) {
- kfree(newmac);
- goto put_ocotp_node;
- }
-
- macaddr = newmac->value;
- if (i) {
- macaddr[5] = (macaddr_low >> 16) & 0xff;
- macaddr[4] = (macaddr_low >> 24) & 0xff;
- macaddr[3] = macaddr1_high & 0xff;
- macaddr[2] = (macaddr1_high >> 8) & 0xff;
- macaddr[1] = (macaddr1_high >> 16) & 0xff;
- macaddr[0] = (macaddr1_high >> 24) & 0xff;
- } else {
- macaddr[5] = macaddr_high & 0xff;
- macaddr[4] = (macaddr_high >> 8) & 0xff;
- macaddr[3] = (macaddr_high >> 16) & 0xff;
- macaddr[2] = (macaddr_high >> 24) & 0xff;
- macaddr[1] = macaddr_low & 0xff;
- macaddr[0] = (macaddr_low >> 8) & 0xff;
- }
-
- of_update_property(enet_np, newmac);
-
-put_ocotp_node:
- of_node_put(ocotp_np);
-put_enet_node:
- of_node_put(enet_np);
- }
-}
-
static inline void imx6q_enet_init(void)
{
imx6_enet_mac_init("fsl,imx6q-fec", "fsl,imx6q-ocotp");
switch (m4_message) {
case MU_LPM_M4_REQUEST_HIGH_BUS:
request_bus_freq(BUS_FREQ_HIGH);
+#ifdef CONFIG_SOC_IMX6SX
imx6sx_set_m4_highfreq(true);
+#endif
imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX,
MU_LPM_BUS_HIGH_READY_FOR_M4);
m4_freq_low = false;
break;
case MU_LPM_M4_RELEASE_HIGH_BUS:
release_bus_freq(BUS_FREQ_HIGH);
+#ifdef CONFIG_SOC_IMX6SX
imx6sx_set_m4_highfreq(false);
+#endif
imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX,
MU_LPM_M4_FREQ_CHANGE_READY);
m4_freq_low = true;
u32 mmdc_val[MX6_MAX_MMDC_NUM][2];
} __aligned(8);
-unsigned long save_ttbr1(void)
-{
- unsigned long lttbr1;
-
- asm volatile(
- ".align 4\n"
- "mrc p15, 0, %0, c2, c0, 1\n"
- : "=r" (lttbr1)
- );
- return lttbr1;
-}
-
-void restore_ttbr1(unsigned long ttbr1)
-{
- asm volatile(
- ".align 4\n"
- "mcr p15, 0, %0, c2, c0, 1\n"
- : : "r" (ttbr1)
- );
-}
-
void imx6_set_int_mem_clk_lpm(bool enable)
{
u32 val = readl_relaxed(ccm_base + CGPR);
unsigned int console_saved_reg[11] = {0};
static unsigned int ccm_ccgr4, ccm_ccgr6;
+#ifdef CONFIG_SOC_IMX6SX
if (imx_src_is_m4_enabled()) {
if (imx_gpc_is_m4_sleeping() && imx_mu_is_m4_in_low_freq()) {
imx_gpc_hold_m4_in_sleep();
return 0;
}
}
+#endif
switch (state) {
case PM_SUSPEND_STANDBY:
imx6_set_lpm(STOP_POWER_ON);
imx6_set_int_mem_clk_lpm(true);
imx_gpc_pre_suspend(false);
+#ifdef CONFIG_SOC_IMX6SL
if (cpu_is_imx6sl())
imx6sl_set_wait_clk(true);
+#endif
/* Zzz ... */
cpu_do_idle();
+#ifdef CONFIG_SOC_IMX6SL
if (cpu_is_imx6sl())
imx6sl_set_wait_clk(false);
+#endif
imx_gpc_post_resume();
imx6_set_lpm(WAIT_CLOCKED);
break;
return -EINVAL;
}
+#ifdef CONFIG_SOC_IMX6SX
if (imx_src_is_m4_enabled()) {
imx_mu_enable_m4_irqs_in_gic(false);
imx_gpc_release_m4_in_sleep();
}
+#endif
return 0;
}
#define UART_UBRC 0xac
#define UART_UTS 0xb4
-unsigned long iram_tlb_base_addr;
-unsigned long iram_tlb_phys_addr;
+extern unsigned long iram_tlb_base_addr;
+extern unsigned long iram_tlb_phys_addr;
static unsigned int *ocram_saved_in_ddr;
static void __iomem *ocram_base;
/*
* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
struct clk_gate2 *gate = to_clk_gate2(hw);
if (imx_src_is_m4_enabled()) {
+#ifdef CONFIG_SOC_IMX6SX
if (!amp_power_mutex || !shared_mem) {
if (enable)
clk_gate2_do_hardware(gate, enable);
clk_gate2_do_hardware(gate, enable);
imx_sema4_mutex_unlock(amp_power_mutex);
+#endif
} else {
clk_gate2_do_hardware(gate, enable);
}
/*
- * Copyright 2012-2014 Freescale Semiconductor, Inc.
+ * Copyright 2012-2015 Freescale Semiconductor, Inc.
* Copyright 2012 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
struct clk_pfd *pfd = to_clk_pfd(hw);
if (imx_src_is_m4_enabled()) {
+#ifdef CONFIG_SOC_IMX6SX
if (!amp_power_mutex || !shared_mem) {
if (enable)
clk_pfd_do_hardware(pfd, enable);
clk_pfd_do_hardware(pfd, enable);
imx_sema4_mutex_unlock(amp_power_mutex);
+#endif
} else {
clk_pfd_do_hardware(pfd, enable);
}
static void clk_pllv3_do_shared_clks(struct clk_hw *hw, bool enable)
{
if (imx_src_is_m4_enabled()) {
+#ifdef CONFIG_SOC_IMX6SX
if (!amp_power_mutex || !shared_mem) {
if (enable)
clk_pllv3_do_hardware(hw, enable);
clk_pllv3_do_hardware(hw, enable);
imx_sema4_mutex_unlock(amp_power_mutex);
+#endif
} else {
clk_pllv3_do_hardware(hw, enable);
}
projects / linux.git / commitdiff