MLK-11407-8: ARM: dts: i.mx6sx/i.mx6ul: add ldo-bypass support

add ldo-bypass support for i.mx6sx/i.mx6ul boards, remove deprecated wdog reset
way, such as 'fsl,wdog-reset = <1>', and implement it in wdog driver.

Signed-off-by: Robin Gong <b38343@freescale.com>

diff --git a/arch/arm/boot/dts/imx6sx-14x14-arm2.dts b/arch/arm/boot/dts/imx6sx-14x14-arm2.dts
index 0b7bee2..42a903b 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-14x14-arm2.dts
+++ b/arch/arm/boot/dts/imx6sx-14x14-arm2.dts
@@ -201,7 +201,6 @@
        fsl,cpu_pupscr_sw = <0x1>;
        fsl,cpu_pdnscr_iso2sw = <0x1>;
        fsl,cpu_pdnscr_iso = <0x1>;
-       fsl,wdog-reset = <1>; /* watchdog select of reset source */
        fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
 };
 
@@ -372,8 +371,6 @@
                                MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30     0x17059
                                /* SD2_PWROFF */
                                MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
-                               /* WDOG_B reset */
-                               MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY    0x10b0
                        >;
                };
        };
@@ -543,6 +540,12 @@
        status = "okay";
 };
 
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,wdog_b;
+};
+
 &iomuxc {
        audmux {
                pinctrl_audmux_1: audmuxgrp-1 {
@@ -1247,6 +1250,14 @@
 
        };
 
+       wdog {
+               pinctrl_wdog: wdoggrp {
+                       fsl,pins = <
+                               MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0
+                       >;
+               };
+       };
+
        weim {
                pinctrl_weim_cs0_1: weim_cs0grp-1 {
                        fsl,pins = <

diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
index 04460cc..bcef325 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
+++ b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
@@ -128,6 +128,10 @@
        soc-supply = <&sw1c_reg>;
 };
 
+&gpc {
+       fsl,ldo-bypass = <1>;
+};
+
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet1_1>;
@@ -357,7 +361,6 @@
                        fsl,pins = <
                                MX6SX_PAD_SD4_DATA4__GPIO6_IO_18     0x1b0b0
                                MX6SX_PAD_KEY_ROW1__GPIO2_IO_16      0x1b0b0
-                               MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0
                         >;
                };
        };
@@ -517,6 +520,12 @@
        };
 };
 
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,wdog_b;
+};
+
 &iomuxc {
        audmux {
                pinctrl_audmux_1: audmuxgrp-1 {
@@ -1168,6 +1177,14 @@
 
        };
 
+       wdog {
+               pinctrl_wdog: wdoggrp {
+                       fsl,pins = <
+                               MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0
+                       >;
+               };
+       };
+
        weim {
                pinctrl_weim_cs0_1: weim_cs0grp-1 {
                        fsl,pins = <

diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
index 7100547..4218aad 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -12,6 +12,24 @@
        model = "Freescale i.MX6 SoloX SDB RevA Board";
 };
 
+&cpu0 {
+       operating-points = <
+               /* kHz    uV */
+               996000  1250000
+               792000  1175000
+               396000  1075000
+               >;
+       fsl,soc-operating-points = <
+               /* ARM kHz      SOC uV */
+               996000  1175000
+               792000  1175000
+               396000  1175000
+       >;
+       arm-supply = <&sw1a_reg>;
+       soc-supply = <&sw1c_reg>;
+       fsl,arm-soc-shared = <0>;
+};
+
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index ba61832..2125364 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -12,6 +12,25 @@
        model = "Freescale i.MX6 SoloX SDB RevB Board";
 };
 
+&cpu0 {
+       operating-points = <
+               /* kHz    uV */
+               996000  1250000
+               792000  1175000
+               396000  1175000
+       >;
+       fsl,soc-operating-points = <
+               /* ARM kHz      SOC uV */
+               996000  1250000
+               792000  1175000
+               396000  1175000
+       >;
+
+       arm-supply = <&sw1a_reg>;
+       soc-supply = <&sw1a_reg>;
+       fsl,arm-soc-shared = <1>;
+};
+
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index d13b3c0..b0af1a3 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -181,6 +181,11 @@
        status = "okay";
 };
 
+
+&gpc {
+       fsl,ldo-bypass = <1>;
+};
+
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet1>;
@@ -393,6 +398,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_wdog>;
        fsl,ext-reset-output;
+       fsl,wdog_b;
 };
 
 &iomuxc {

diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts
index 521cedb..d31bd3c 100644 (file)
--- a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts
@@ -164,7 +164,6 @@
        fsl,cpu_pupscr_sw = <0x0>;
        fsl,cpu_pdnscr_iso2sw = <0x1>;
        fsl,cpu_pdnscr_iso = <0x1>;
-       fsl,wdog-reset = <1>; /* watchdog select of reset source */
        fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
 };
 

diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
index fdb7fa7..5654426 100644 (file)
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -235,7 +235,6 @@
        fsl,cpu_pupscr_sw = <0x0>;
        fsl,cpu_pdnscr_iso2sw = <0x1>;
        fsl,cpu_pdnscr_iso = <0x1>;
-       fsl,wdog-reset = <1>; /* watchdog select of reset source */
        fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
 };
 
@@ -260,6 +259,41 @@
        };
 };
 
+&i2c2 {
+       clock_frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       codec: wm8960@1a {
+               compatible = "wlf,wm8960";
+               reg = <0x1a>;
+               clocks = <&clks IMX6UL_CLK_SAI2>;
+               clock-names = "mclk";
+               wlf,shared-lrclk;
+       };
+
+       ov5640: ov5640@3c {
+               compatible = "ovti,ov5640";
+               reg = <0x3c>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_csi1>;
+               clocks = <&clks IMX6UL_CLK_CSI>;
+               clock-names = "csi_mclk";
+               pwn-gpios = <&gpio_spi 6 1>;
+               rst-gpios = <&gpio_spi 5 0>;
+               csi_id = <0>;
+               mclk = <24000000>;
+               mclk_source = <0>;
+               status = "disabled";
+               port {
+                       ov5640_ep: endpoint {
+                               remote-endpoint = <&csi1_ep>;
+                       };
+               };
+       };
+};
+
 &lcdif {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_lcdif_dat
@@ -403,6 +437,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_wdog>;
        fsl,ext-reset-output;
+       fsl,wdog_b;
 };
 
 &iomuxc {
@@ -674,4 +709,15 @@
                        MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
                >;
        };
+
+       pinctrl_sim2_1: sim2grp-1 {
+               fsl,pins = <
+                       MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
+                       MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
+                       MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
+                       MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
+                       MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
+                       MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
+               >;
+       };
 };