commit
65c558ec270003e8e99cb58c940d3b913d08fa39
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Tue May 15 08:47:19 2018 +0800
arm64: dts: ls1012a: correct the register range of dcfg
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit
8f7b4cded4ea1fca53516ae8f5d5bc89af291f26
Author: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Date: Mon May 7 11:52:04 2018 +0530
arm64: dts: ls1012a: Add LS1012A-FRWY board support
LS1012A-FRWY is a different design from LS1012A-FRDM,
but has some common SoC features. Key feature on this
board is 2x1G SGMII PFE MAC, Micro SD, USB 3.0, DDR,
QuadSPI, Audio, UART.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
commit
94fc77837b3b6f4213a49b29ddc3e09e38ae5fbb
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon Apr 2 16:16:47 2018 +0800
arm64: dts: ls1012a: add dts entry for A-010650
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit
4fdc98a03492b732a48426a4180f7d6a36847e71
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Wed Nov 1 10:31:47 2017 +0800
arm64: dts: ls1012a: correct the i2c clock to 1/4 platform pll
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit
bb534725996b92aff853a4dee43738629fd4ac08
Author: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Date: Wed Nov 29 06:31:23 2017 +0530
arm64: dts: freescale: ls1012a: Disable PCIe node as default
Keep PCIe node in "disabled" status as SoC default.
Only enable it for boards with PCIe circuit designed,
such as LS1012ARDB and LS1012AQDS.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
commit
6b9a3244baba2c5126f349800ecaad83ba97ee47
Author: Calvin Johnson <calvin.johnson@nxp.com>
Date: Mon Oct 16 12:25:19 2017 +0530
arm64: dts: freescale: ls1012a: fix RGMII tx delay issue
Recently logic to enable RGMII tx delay was changed by
below patch.
https://patchwork.kernel.org/patch/
9447581/
Based on the patch, enabling tx delay again using rgmii-txid.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
commit
1e17e247088f6e2c08041559e38053b70a9d2bbe
Author: Calvin Johnson <calvin.johnson@nxp.com>
Date: Sat Sep 16 14:20:23 2017 +0530
arm64: dts: freescale: ls1012a: update with pppfe support
Update ls1012a dtsi and platform dts files with
support for ppfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
commit
ed9c51239461fe0322da2e93f50033ea0d05bc4f
Author: Chenhui Zhao <chenhui.zhao@nxp.com>
Date: Fri May 5 17:45:15 2017 +0800
arm64: dts: ls1012a: add ftm0 node
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
model = "LS1012A Freedom Board";
compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
+
&sai2 {
status = "okay";
};
&sata {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+ reg = <0>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+
+};
model = "LS1012A QDS Board";
compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
+&pcie1 {
+ status = "okay";
+};
+
&dspi {
bus-num = <0>;
status = "okay";
};
};
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x2>;
+ phy-mode = "sgmii-2500";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x3>;
+ phy-mode = "sgmii-2500";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
+
&sai2 {
status = "okay";
};
&sata {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+ reg = <0>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+
+};
/ {
model = "LS1012A RDB Board";
compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+};
+
+&pcie1 {
+ status = "okay";
};
&duart0 {
&sata {
status = "okay";
};
+
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "rgmii-txid";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+ reg = <0>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+
+};
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1012a-dcfg",
"syscon";
- reg = <0x0 0x1ee0000 0x0 0x10000>;
+ reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
};
i2c0: i2c@2180000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
+ scl-gpios = <&gpio0 13 0>;
status = "disabled";
};
};
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ pfe_reserved: packetbuffer@83400000 {
+ reg = <0 0x83400000 0 0xc00000>;
+ };
+ };
+
+ pfe: pfe@04000000 {
+ compatible = "fsl,pfe";
+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
+ reg-names = "pfe", "pfe-ddr";
+ fsl,pfe-num-interfaces = <0x2>;
+ interrupts = <0 172 0x4>, /* HIF interrupt */
+ <0 173 0x4>, /*HIF_NOCPY interrupt */
+ <0 174 0x4>; /* WoL interrupt */
+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
+ memory-region = <&pfe_reserved>;
+ fsl,pfe-scfg = <&scfg 0>;
+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "pfe";
+
+ status = "okay";
+ pfe_mac0: ethernet@0 {
+ };
+
+ pfe_mac1: ethernet@1 {
+ };
+ };
+
firmware {
optee {
compatible = "linaro,optee-tz";
projects / linux.git / commitdiff