MLK-11344-10: ARM: dts: imx7d-12x12-lpddr3-arm2-ecspi: add ecspi support

Enable ecspi dtb for imx7d-12x12-lpddr3-arm2 board.

Signed-off-by: Robin Gong <b38343@freescale.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 2d68805..1f8c968 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -435,7 +435,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
        imx7s-colibri-eval-v3.dtb \
        imx7s-warp.dtb \
        imx7d-12x12-lpddr3-arm2.dtb \
-       imx7d-12x12-lpddr3-arm2-m4.dtb
+       imx7d-12x12-lpddr3-arm2-m4.dtb \
+       imx7d-12x12-lpddr3-arm2-ecspi.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
        ls1021a-qds.dtb \
        ls1021a-twr.dtb

diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts
new file mode 100644 (file)
index 0000000..b74863f
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7d-12x12-lpddr3-arm2.dts"
+
+&epdc {
+        status = "disabled";
+};
+
+&ecspi1{
+        status = "okay";
+};
+
+/*
+ * pin conflict with ecspi1
+ * default hog setting conflicts with ECSPI1 MOSI and MISO
+ * EPDC PWRCTRL conflicts with ECSPI1 CS pin
+ */
+&iomuxc {
+       pinctrl-0 = <&pinctrl_hog_1>;
+};

diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts
index 71c4cfb..137c069 100644 (file)
--- a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts
+++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts
@@ -80,6 +80,22 @@
        arm-supply = <&sw1a_reg>;
 };
 
+&ecspi1 {
+       fsl,spi-num-chipselects = <1>;
+       cs-gpios = <&gpio4 19 0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
+       status = "disabled";
+
+       spi_flash1: m25p80@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "st,m25p32";
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+       };
+};
+
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet1>;
@@ -237,6 +253,21 @@
        pinctrl-0 = <&pinctrl_hog_1>;
 
        imx7d-12x12-lpddr3-arm2 {
+
+               pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
+                       fsl,pins = <
+                               MX7D_PAD_ECSPI1_SS0__GPIO4_IO19     0x2
+                       >;
+               };
+
+               pinctrl_ecspi1_1: ecspi1grp-1 {
+                       fsl,pins = <
+                               MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO   0x2
+                               MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI   0x2
+                               MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK   0x2
+                       >;
+               };
+
                pinctrl_enet1: enet1grp {
                        fsl,pins = <
                                MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
@@ -281,7 +312,6 @@
                                MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21  0x80000000
                                MX7D_PAD_ECSPI2_MISO__GPIO4_IO22  0x80000000
                                MX7D_PAD_ECSPI2_SS0__GPIO4_IO23   0x80000000
-                               MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17  0x80000000
                                MX7D_PAD_SD1_RESET_B__GPIO5_IO2   0x17059
                                MX7D_PAD_SD1_CD_B__GPIO5_IO0      0x17059
                                MX7D_PAD_SD1_WP__GPIO5_IO1        0x17059