MLK-16919-4 dts: iMX8MQ: add csi/mipi_csi/camera support

Add CSI bridge, MIPI CSI, and camera support

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-fbdev.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-fbdev.dts
index 5ecaba0..fdeb5c8 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-fbdev.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-fbdev.dts
@@ -112,10 +112,47 @@
        assigned-clock-rates = <786432000>;
 };
 
+&csi1_bridge {
+       fsl,mipi-mode;
+       status = "okay";
+
+       port {
+               csi1_ep: endpoint {
+                       remote-endpoint = <&csi1_mipi_ep>;
+               };
+       };
+};
+
+&csi2_bridge {
+       fsl,mipi-mode;
+       status = "disabled";
+
+       port {
+               csi2_ep: endpoint {
+                       remote-endpoint = <&csi2_mipi_ep>;
+               };
+       };
+};
+
 &iomuxc {
        pinctrl-names = "default";
 
        imx8mq-evk {
+               pinctrl_csi1: csi1grp {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x19
+                               MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x19
+                               MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x59
+                       >;
+               };
+               pinctrl_csi2: csi2grp {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5               0x19
+                               MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x19
+                               MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x59
+                       >;
+               };
+
                pinctrl_fec1: fec1grp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC         0x3
@@ -470,6 +507,47 @@
                port-type = "drp";
                default-role = "sink";
        };
+
+       ov5640_mipi: ov5640_mipi@3c {
+               compatible = "ovti,ov5640_mipi";
+               reg = <0x3c>;
+               status = "okay";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_csi1>;
+               clocks = <&clk IMX8MQ_CLK_DUMMY>;
+               clock-names = "csi_mclk";
+               csi_id = <0>;
+               pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+               rst-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+               mclk = <24000000>;
+               mclk_source = <0>;
+               port {
+                       ov5640_mipi1_ep: endpoint {
+                               remote-endpoint = <&mipi1_sensor_ep>;
+                       };
+               };
+       };
+
+       ov5640_mipi2: ov5640_mipi2@3c {
+               compatible = "ovti,ov5640_mipi";
+               reg = <0x3c>;
+               status = "disabled";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_csi2>;
+               clocks = <&clk IMX8MQ_CLK_DUMMY>;
+               clock-names = "csi_mclk";
+               csi_id = <0>;
+               pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+               rst-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+               /*AVDD-supply = <&vgen6_reg>;*/
+               mclk = <24000000>;
+               mclk_source = <0>;
+               port {
+                       ov5640_mipi2_ep: endpoint {
+                               remote-endpoint = <&mipi2_sensor_ep>;
+                       };
+               };
+       };
 };
 
 &hdmi {
@@ -484,6 +562,38 @@
        status = "disabled";
 };
 
+&mipi_csi_1 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+       port {
+               mipi1_sensor_ep: endpoint1 {
+                       remote-endpoint = <&ov5640_mipi1_ep>;
+                       data-lanes = <1 2>;
+               };
+
+               csi1_mipi_ep: endpoint2 {
+                       remote-endpoint = <&csi1_ep>;
+               };
+       };
+};
+
+&mipi_csi_2 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "disabled";
+       port {
+               mipi2_sensor_ep: endpoint1 {
+                       remote-endpoint = <&ov5640_mipi2_ep>;
+                       data-lanes = <1 2>;
+               };
+
+               csi2_mipi_ep: endpoint2 {
+                       remote-endpoint = <&csi2_ep>;
+               };
+       };
+};
+
 &pcie0{
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
index eada06c..09d7c8b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
@@ -28,6 +28,8 @@
        #size-cells = <2>;
 
        aliases {
+               csi0 = &mipi_csi_1;
+               csi1 = &mipi_csi_2;
                ethernet0 = &fec1;
                serial0 = &uart1;
                serial1 = &uart2;
@@ -502,6 +504,66 @@
                status = "disabled";
        };
 
+       csi1_bridge: csi1_bridge@30a90000 {
+               compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";
+               reg = <0x0 0x30a90000 0x0 0x10000>;
+               interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8MQ_CLK_DUMMY>,
+                       <&clk IMX8MQ_CLK_CSI1_ROOT>,
+                       <&clk IMX8MQ_CLK_DUMMY>;
+               clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+               status = "disabled";
+       };
+
+       csi2_bridge: csi2_bridge@30b80000 {
+               compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";
+               reg = <0x0 0x30b80000 0x0 0x10000>;
+               interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8MQ_CLK_DUMMY>,
+                       <&clk IMX8MQ_CLK_CSI2_ROOT>,
+                       <&clk IMX8MQ_CLK_DUMMY>;
+               clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+               status = "disabled";
+       };
+
+       mipi_csi_1: mipi_csi1@30a70000 {
+               compatible = "fsl,mxc-mipi-csi2_yav";
+               reg = <0x0 0x30a70000 0x0 0x1000>; /* MIPI CSI1 Controller base addr */
+               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8MQ_CLK_DUMMY>,
+                               <&clk IMX8MQ_CLK_CSI1_CORE_DIV>,
+                               <&clk IMX8MQ_CLK_CSI1_ESC_DIV>,
+                               <&clk IMX8MQ_CLK_CSI1_PHY_REF_DIV>;
+               clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
+               assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE_DIV>,
+                                 <&clk IMX8MQ_CLK_CSI1_PHY_REF_DIV>,
+                                 <&clk IMX8MQ_CLK_CSI1_ESC_DIV>;
+               assigned-clock-rates = <133000000>, <100000000>, <66000000>;
+               power-domains = <&mipi_csi1_pd>;
+               csis-phy-reset = <&src 0x4c 7>;
+               phy-gpr = <&gpr 0x88>;
+               status = "disabled";
+       };
+
+       mipi_csi_2: mipi_csi2@30b60000 {
+               compatible = "fsl,mxc-mipi-csi2_yav";
+               reg = <0x0 0x30b60000 0x0 0x1000>; /* MIPI CSI2 Controller base addr */
+               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8MQ_CLK_DUMMY>,
+                               <&clk IMX8MQ_CLK_CSI2_CORE_DIV>,
+                               <&clk IMX8MQ_CLK_CSI2_ESC_DIV>,
+                               <&clk IMX8MQ_CLK_CSI2_PHY_REF_DIV>;
+               clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
+               assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE_DIV>,
+                                 <&clk IMX8MQ_CLK_CSI2_PHY_REF_DIV>,
+                                 <&clk IMX8MQ_CLK_CSI2_ESC_DIV>;
+               assigned-clock-rates = <133000000>, <100000000>, <66000000>;
+               power-domains = <&mipi_csi2_pd>;
+               csis-phy-reset = <&src 0x50 7>;
+               phy-gpr = <&gpr 0xa4>;
+               status = "disabled";
+       };
+
        mipi_dsi: mipi_dsi@30A00000 {
                compatible = "fsl,imx8mq-mipi-dsi";
                reg = <0x0 0x30a00000 0x0 0x10000>;     /* DSI registers */