MLK-16973-6 arm64: dtsi: fsl-imx8qm: Add lvds0/1_pwm nodes

This patch adds lvds0/1_pwm device tree nodes for the i.MX8QM SoC.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index d1d60ea..1f4f331 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -1438,6 +1438,19 @@
                };
        };
 
+       lvds0_pwm: pwm@56244000 {
+               compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+               reg = <0x0 0x56244000 0 0x1000>;
+               clocks = <&clk IMX8QM_LVDS0_PWM0_IPG_CLK>,
+                        <&clk IMX8QM_LVDS0_PWM0_CLK>;
+               clock-names = "ipg", "per";
+               assigned-clocks = <&clk IMX8QM_LVDS0_PWM0_CLK>;
+               assigned-clock-rates = <24000000>;
+               #pwm-cells = <2>;
+               power-domains = <&pd_lvds0_pwm>;
+               status = "disabled";
+       };
+
        dpu2_intsteer: dpu_intsteer@57000000 {
                compatible = "fsl,imx8qm-dpu-intsteer", "syscon";
                reg = <0x0 0x57000000 0x0 0x10000>;
@@ -1664,6 +1677,19 @@
                };
        };
 
+       lvds1_pwm: pwm@57244000 {
+               compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+               reg = <0x0 0x57244000 0 0x1000>;
+               clocks = <&clk IMX8QM_LVDS1_PWM0_IPG_CLK>,
+                        <&clk IMX8QM_LVDS1_PWM0_CLK>;
+               clock-names = "ipg", "per";
+               assigned-clocks = <&clk IMX8QM_LVDS1_PWM0_CLK>;
+               assigned-clock-rates = <24000000>;
+               #pwm-cells = <2>;
+               power-domains = <&pd_lvds1_pwm>;
+               status = "disabled";
+       };
+
        camera {
                compatible = "fsl,mxc-md", "simple-bus";
                #address-cells = <2>;