#ifdef CONFIG_ARCH_MXC_ARM64
sc_ipc_t ipc_handle;
#endif
+ bool wakeup;
/* Selects the clock source to CAN Protocol Engine (PE), 1 by default*/
u32 clk_src;
if (err)
goto out_free_irq;
+ device_set_wakeup_capable(priv->dev, priv->wakeup);
+
can_led_event(dev, CAN_LED_EVENT_OPEN);
can_rx_offload_enable(&priv->offload);
close_candev(dev);
+ device_set_wakeup_capable(priv->dev, false);
+
can_led_event(dev, CAN_LED_EVENT_STOP);
pm_runtime_put(priv->dev);
int err, irq;
u32 clock_freq = 0;
u32 clk_src = 1;
- int wakeup = 1;
reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
devm_can_led_init(dev);
+ priv->wakeup = true;
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_TIMESTAMP_SUPPORT_FD) {
err = imx8_sc_ipc_fetch(pdev);
if (err) {
- wakeup = 0;
+ priv->wakeup = false;
dev_dbg(&pdev->dev, "failed to fetch scu ipc\n");
}
} else if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG) {
err = flexcan_of_parse_stop_mode(pdev);
if (err) {
- wakeup = 0;
+ priv->wakeup = false;
dev_dbg(&pdev->dev, "failed to parse stop-mode\n");
}
}
- device_set_wakeup_capable(&pdev->dev, wakeup);
-
pm_runtime_put(&pdev->dev);
dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",