LF-2340 arm64: dts: imx8dxl-evk: add eqos and enet support

Add eqos and enet support for imx8dxl evk board.

Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index ce95f21..59429b2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-dom0.dtb imx8qm-mek-domu.dtb \
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb \
+                         imx8dxl-evk-enet0.dtb imx8dxl-evk-enet0-tja1100.dtb \
                          imx8dxl-evk-rpmsg.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8dxl-phantom-mek.dtb \
                          imx8dxl-phantom-mek-rpmsg.dtb

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts
new file mode 100644 (file)
index 0000000..b1de121
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8dxl-evk-enet0.dts"
+
+&ethphy1 {
+       status = "disabled";
+};
+
+&fec1 {
+       pinctrl-0 = <&pinctrl_fec1_rmii>;
+       clocks = <&enet0_lpcg 4>,
+                <&enet0_lpcg 2>,
+                <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>,
+                <&enet0_lpcg 0>,
+                <&enet0_lpcg 1>;
+       phy-mode = "rmii";
+       phy-handle = <&ethphy2>;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy2: ethernet-phy@2 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <2>;
+                       tja110x,refclk_in;
+               };
+       };
+};
+
+&iomuxc {
+       pinctrl_fec1_rmii: fec1rmiigrp {
+               fsl,pins = <
+                       IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD   0x000014a0
+                       IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD   0x000014a0
+                       IMX8DXL_ENET0_MDC_CONN_ENET0_MDC                        0x06000020
+                       IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO                      0x06000020
+                       IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT          0x06000060
+                       IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL      0x00000060
+                       IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0          0x00000060
+                       IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1          0x00000060
+                       IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL      0x00000060
+                       IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0          0x00000060
+                       IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1          0x00000060
+                       IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER          0x00000060
+               >;
+       };
+};
+
+&max7322 {
+       status = "disabled";
+};
+
+&reg_fec1_io {
+       status = "disabled";
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts
new file mode 100644 (file)
index 0000000..394cdc8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8dxl-evk.dts"
+
+&reg_fec1_sel {
+       status = "okay";
+};
+
+&reg_fec1_io {
+       status = "okay";
+};
+
+&eqos {
+       status = "disabled";
+};
+
+&fec1 {
+       status = "okay";
+};
+
+&max7322 {
+       status = "okay";
+};
+
+&usdhc2 {
+       status = "disabled";
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 3a01f50..03c26af 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -88,6 +88,27 @@
                #reset-cells = <0>;
        };
 
+       reg_fec1_sel: regfec1_sel {
+               compatible = "regulator-fixed";
+               regulator-name = "fec1_supply";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
+               regulator-always-on;
+               status = "disabled";
+       };
+
+       reg_fec1_io: regfec1_io {
+               compatible = "regulator-fixed";
+               regulator-name = "fec1_io_supply";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               regulator-always-on;
+               status = "disabled";
+       };
+
        reg_usdhc2_vmmc: usdhc2-vmmc {
                compatible = "regulator-fixed";
                regulator-name = "SD1_SPWR";
@@ -103,6 +124,60 @@
        status = "okay";
 };
 
+&eqos {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_eqos>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       nvmem-cells = <&fec_mac1>;
+       nvmem-cell-names = "mac-address";
+       snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
+       snps,reset-delays-us = <10 20 200000>;
+       status = "okay";
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+                       eee-broken-1000t;
+                       at803x,eee-disabled;
+                       at803x,vddio-1p8v;
+               };
+
+       };
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       phy-mode = "rgmii-txid";
+       phy-handle = <&ethphy1>;
+       fsl,magic-packet;
+       fsl,rgmii_rxc_dly;
+       nvmem-cells = <&fec_mac0>;
+       nvmem-cell-names = "mac-address";
+       phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <150>;
+       status = "disabled";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+                       at803x,eee-disabled;
+                       at803x,vddio-1p8v;
+               };
+       };
+};
+
 &imx8dxl_cm4 {
        memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>,
                        <&vdev1vring0>, <&vdev1vring1>;
@@ -313,6 +388,46 @@
                >;
        };
 
+       pinctrl_eqos: eqosgrp {
+               fsl,pins = <
+                       IMX8DXL_ENET0_MDC_CONN_EQOS_MDC                         0x06000020
+                       IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO                       0x06000020
+                       IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL       0x06000020
+                       IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC             0x06000020
+                       IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0           0x06000020
+                       IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1           0x06000020
+                       IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2           0x06000020
+                       IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3           0x06000020
+                       IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC             0x06000020
+                       IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL       0x06000020
+                       IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0           0x06000020
+                       IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1           0x06000020
+                       IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2           0x06000020
+                       IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3           0x06000020
+               >;
+       };
+
+       pinctrl_fec1: fec1grp {
+               fsl,pins = <
+                       IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD           0x000014a0
+                       IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD           0x000014a0
+                       IMX8DXL_ENET0_MDC_CONN_ENET0_MDC                        0x06000020
+                       IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO                      0x06000020
+                       IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL      0x00000060
+                       IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC            0x00000060
+                       IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0          0x00000060
+                       IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1          0x00000060
+                       IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2          0x00000060
+                       IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3          0x00000060
+                       IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC            0x00000060
+                       IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL      0x00000060
+                       IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0          0x00000060
+                       IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1          0x00000060
+                       IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2          0x00000060
+                       IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3          0x00000060
+               >;
+       };
+
        pinctrl_i2c2: i2c2grp {
                fsl,pins = <
                        IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA          0x06000021