clk: meson: remove special gp0 lock loop

After testing, it appears that the gxl (and axg) does not require the
special locking/reset loop which was initially added for it.

All the values present in the gxl table can locked with the simple lock
checking loop.

The change switches the gxl and axg gp0 back to the simple lock checking
loop and removes the code no longer required.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 8226b82..4f13929 100644 (file)
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -231,7 +231,6 @@ static struct clk_regmap axg_gp0_pll = {
                .table = axg_gp0_pll_rate_table,
                .init_regs = axg_gp0_init_regs,
                .init_count = ARRAY_SIZE(axg_gp0_init_regs),
-               .flags = CLK_MESON_PLL_LOCK_LOOP_RST,
        },
        .hw.init = &(struct clk_init_data){
                .name = "gp0_pll",

diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index f3d9097..0b9b442 100644 (file)
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -121,19 +121,9 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw)
 {
        struct clk_regmap *clk = to_clk_regmap(hw);
        struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
-       int delay = pll->flags & CLK_MESON_PLL_LOCK_LOOP_RST ?
-               100 : 24000000;
+       int delay = 24000000;
 
        do {
-               /* Specific wait loop for GXL/GXM GP0 PLL */
-               if (pll->flags & CLK_MESON_PLL_LOCK_LOOP_RST) {
-                       /* Procedure taken from the vendor kernel */
-                       meson_parm_write(clk->map, &pll->rst, 1);
-                       udelay(10);
-                       meson_parm_write(clk->map, &pll->rst, 0);
-                       mdelay(1);
-               }
-
                /* Is the clock locked now ? */
                if (meson_parm_read(clk->map, &pll->l))
                        return 0;

diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 8d8fe60..ebd88af 100644 (file)
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -82,8 +82,6 @@ struct pll_rate_table {
                .frac           = (_frac),                              \
        }                                                               \
 
-#define CLK_MESON_PLL_LOCK_LOOP_RST    BIT(0)
-
 struct meson_clk_pll_data {
        struct parm m;
        struct parm n;

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 3cd07f9..ac48eef 100644 (file)
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -475,7 +475,6 @@ static struct clk_regmap gxl_gp0_pll = {
                .table = gxl_gp0_pll_rate_table,
                .init_regs = gxl_gp0_init_regs,
                .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
-               .flags = CLK_MESON_PLL_LOCK_LOOP_RST,
        },
        .hw.init = &(struct clk_init_data){
                .name = "gp0_pll",