MLK-13344-01 ARM: imx: Change AXI and AHB clock rate on imx6sll

Increase the AXI and AHB clock rate on i.MX6SLL according to
the RM to improve the system bus performance.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c
index e4e6b6e..cd16c2d 100644 (file)
--- a/drivers/clk/imx/clk-imx6sll.c
+++ b/drivers/clk/imx/clk-imx6sll.c
@@ -356,6 +356,16 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
                clk_prepare_enable(clks[IMX6SLL_CLK_USBPHY2_GATE]);
        }
 
+       /* Lower the AHB clock rate before changing the clock source. */
+       imx_clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000);
+
+       /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
+       imx_clk_set_parent(clks[IMX6SLL_CLK_PERIPH_CLK2_SEL], clks[IMX6SLL_CLK_PLL3_USB_OTG]);
+       imx_clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_CLK2]);
+       imx_clk_set_parent(clks[IMX6SLL_CLK_PERIPH_PRE], clks[IMX6SLL_CLK_PLL2_BUS]);
+       imx_clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_PRE]);
+
+       imx_clk_set_rate(clks[IMX6SLL_CLK_AHB], 132000000);
 }
 
 CLK_OF_DECLARE(imx6sll, "fsl,imx6sll-ccm", imx6sll_clocks_init);