pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
+ phy-reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ phy-reset-post-delay = <150>;
+ phy-reset-duration = <10>;
fsl,magic-packet;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
- ethphy0: ethernet-phy@0 {
+ ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
+ reg = <4>;
};
};
};
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x19
>;
};
#define PHY_ANEG_TIMEOUT 20000
#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_FEC_MXC_PHYADDR 4
#define IMX_FEC_BASE 0x30BE0000
#endif