LF-148 arm: dts: imx7ulp: set the sdhc clock sourced from apll_pfd1

imx7ulp need to support emmc hs400 mode, this mode need the sdhc clock
set near 400MHz, so that hs400 mode can work at near 200MHz, to get
the best performance. And also due to the I/O limitation, HS400 can only
work stable when the card clock rate is less than 176.4MHz. So this patch
change the sdhc clock sourced from apll_pfd1, and config the apll_pfd1
at 352.8MHz.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
[ Aisheng: moved the change into board dts ]
Sign-off-by: Dong Aisheng <aisheng.dong@nxp.com>

diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
index 8495391..2e3c453 100644 (file)
--- a/arch/arm/boot/dts/imx7ulp-evk.dts
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -410,8 +410,9 @@
 };
 
 &usdhc0 {
-       assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
-       assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
+       assigned-clocks = <&scg1 IMX7ULP_CLK_APLL_PFD1>, <&pcc2 IMX7ULP_CLK_USDHC0>;
+       assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD1>;
+       assigned-clock-rates = <0>, <352800000>;
        pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
        pinctrl-0 = <&pinctrl_usdhc0>;
        pinctrl-1 = <&pinctrl_usdhc0>;
@@ -425,6 +426,9 @@
 };
 
 &usdhc1 {
+       assigned-clocks = <&scg1 IMX7ULP_CLK_APLL_PFD1>, <&pcc2 IMX7ULP_CLK_USDHC1>;
+       assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD1>;
+       assigned-clock-rates = <0>, <352800000>;
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&pinctrl_usdhc1>;
        pinctrl-1 = <&pinctrl_usdhc1>;