--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "fsl-imx8-ca53.dtsi"
+#include "fsl-imx8-ca72.dtsi"
+#include <dt-bindings/clock/imx8qm-clock.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_hsio.h>
+#include <dt-bindings/soc/imx8_pd.h>
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "fsl,imx8qm";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ dpu0 = &dpu1;
+ ethernet0 = &fec1;
+ dsiphy0 = &mipi_dsi_phy1;
+ mipidsi0 = &mipi_dsi1;
+ ldb0 = &ldb1;
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial3 = &lpuart3;
+ serial4 = &lpuart4;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &gpio5;
+ gpio6 = &gpio6;
+ gpio7 = &gpio7;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ usb0 = &usbotg1;
+ usbphy0 = &usbphy1;
+ usb1 = &usbotg3;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c6 = &i2c1_lvds0;
+ spi0 = &flexspi0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ /* DRAM space - 1, size : 1 GB DRAM */
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * reserved-memory layout
+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
+ * Shouldn't be used at A core and Linux side.
+ *
+ */
+
+ decoder_boot: decoder_boot@0x84000000 {
+ no-map;
+ reg = <0 0x84000000 0 0x2000000>;
+ };
+ encoder_boot: encoder_boot@0x86000000 {
+ no-map;
+ reg = <0 0x86000000 0 0x400000>;
+ };
+ rpmsg_reserved: rpmsg@0x90000000 {
+ no-map;
+ reg = <0 0x90000000 0 0x400000>;
+ };
+ rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0 0x90400000 0 0x1C00000>;
+ };
+ decoder_rpc: decoder_rpc@0x92000000 {
+ no-map;
+ reg = <0 0x92000000 0 0x200000>;
+ };
+ encoder_rpc: encoder_rpc@0x92200000 {
+ no-map;
+ reg = <0 0x92200000 0 0x200000>;
+ };
+ dsp_reserved: dsp@0x92400000 {
+ no-map;
+ reg = <0 0x92400000 0 0x2000000>;
+ };
+ encoder_reserved: encoder_reserved@0x94400000 {
+ no-map;
+ reg = <0 0x94400000 0 0x800000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x3c000000>;
+ alloc-ranges = <0 0x96000000 0 0x3c000000>;
+ linux,cma-default;
+ };
+
+ };
+
+ gic: interrupt-controller@51a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+ <0x0 0x51b00000 0 0xC0000>, /* GICR */
+ <0x0 0x52000000 0 0x2000>, /* GICC */
+ <0x0 0x52010000 0 0x1000>, /* GICH */
+ <0x0 0x52020000 0 0x20000>; /* GICV */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-parent = <&gic>;
+ };
+
+ mu8: mu@5d230000 {
+ compatible = "fsl,imx-m4-mu";
+ reg = <0x0 0x5d230000 0x0 0x10000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_lsio_mu8a>;
+ status = "okay";
+ };
+
+ mu9: mu@5d240000 {
+ compatible = "fsl,imx-m4-mu";
+ reg = <0x0 0x5d240000 0x0 0x10000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_lsio_mu9a>;
+ status = "okay";
+ };
+
+ mu: mu@5d1c0000 {
+ compatible = "fsl,imx8-mu";
+ reg = <0x0 0x5d1c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ #mbox-cells = <4>;
+ status = "okay";
+
+ clk: clk {
+ compatible = "fsl,imx8qm-clk";
+ #clock-cells = <1>;
+ };
+
+ iomuxc: iomuxc {
+ compatible = "fsl,imx8qm-iomuxc";
+ };
+ };
+
+ mu13: mu13@5d280000 {
+ compatible = "fsl,imx8-mu-dsp";
+ reg = <0x0 0x5d280000 0x0 0x10000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,dsp_ap_mu_id = <13>;
+ status = "okay";
+ };
+
+ mu_m0: mu_m0@2d000000 {
+ compatible = "fsl,imx8-mu0-vpu-m0";
+ reg = <0x0 0x2d000000 0x0 0x20000>;
+ interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <16>;
+ status = "disabled";
+ };
+
+ mu1_m0: mu1_m0@2d020000 {
+ compatible = "fsl,imx8-mu1-vpu-m0";
+ reg = <0x0 0x2d020000 0x0 0x20000>;
+ interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <17>;
+ status = "disabled";
+ };
+
+ mu2_m0: mu2_m0@2d040000 {
+ compatible = "fsl,imx8-mu2-vpu-m0";
+ reg = <0x0 0x2d040000 0x0 0x20000>;
+ interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <18>;
+ status = "disabled";
+ };
+
+ vpu_decoder: vpu_decoder@2c000000 {
+ compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
+ boot-region = <&decoder_boot>;
+ rpc-region = <&decoder_rpc>;
+ reg = <0x0 0x2c000000 0x0 0x1000000>;
+ reg-names = "vpu_regs";
+ reg-csr = <0x2d080000>;
+ status = "disabled";
+ };
+
+ vpu_encoder: vpu_encoder@2d000000 {
+ compatible = "nxp,imx8qm-b0-vpuenc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot-region = <&encoder_boot>;
+ rpc-region = <&encoder_rpc>;
+ reserved-region = <&encoder_reserved>;
+ reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/
+ <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/
+ reg-names = "vpu_regs";
+ reg-rpc-system = <0x40000000>;
+
+ resolution-max = <1920 1080>;
+ fps-max = <120>;
+ status = "disabled";
+
+ core0@1020000 {
+ compatible = "fsl,imx8-mu1-vpu-m0";
+ reg = <0x1020000 0x20000>;
+ reg-csr = <0x1090000 0x10000>;
+ interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <17>;
+ fw-buf-size = <0x200000>;
+ rpc-buf-size = <0x80000>;
+ print-buf-size = <0x80000>;
+ };
+ core1@1040000 {
+ compatible = "fsl,imx8-mu2-vpu-m0";
+ reg = <0x1040000 0x20000>;
+ reg-csr = <0x10a0000 0x10000>;
+ interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <18>;
+ fw-buf-size = <0x200000>;
+ rpc-buf-size = <0x80000>;
+ print-buf-size = <0x80000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+ clock-frequency = <8000000>;
+ interrupt-parent = <&gic>;
+ };
+
+ smmu: iommu@51400000 {
+ compatible = "arm,mmu-500";
+ interrupt-parent = <&gic>;
+ reg = <0 0x51400000 0 0x40000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ interrupts = <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
+ };
+
+ cci: cci@52090000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x52090000 0 0x1000>;
+ ranges = <0 0 0x52090000 0x10000>;
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1",
+ "arm,cci-400-pmu";
+ reg = <0x9000 0x4000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+ };
+
+ #include "fsl-imx8qm-device.dtsi"
+};
+
+&A53_0 {
+ operating-points = <
+ /* kHz uV */
+ /* voltage is maintained by SCFW, so no need here */
+ 1200000 0
+ 1104000 0
+ 900000 0
+ 600000 0
+ >;
+ clocks = <&clk IMX8QM_A53_DIV>;
+ clock-latency = <61036>;
+ #cooling-cells = <2>;
+ /delete-property/ cpu-idle-states;
+};
+
+&A72_0 {
+ operating-points = <
+ /* kHz uV */
+ /* voltage is maintained by SCFW, so no need here */
+ 1596000 0
+ 1296000 0
+ 1056000 0
+ 600000 0
+ >;
+ clocks = <&clk IMX8QM_A72_DIV>;
+ clock-latency = <61036>;
+ #cooling-cells = <2>;
+ /delete-property/ cpu-idle-states;
+};
+
+&A53_1 {
+ /delete-property/ cpu-idle-states;
+};
+
+&A53_2 {
+ /delete-property/ cpu-idle-states;
+};
+
+&A53_3 {
+ /delete-property/ cpu-idle-states;
+};
+
+&A72_1 {
+ /delete-property/ cpu-idle-states;
+};
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "fsl-imx8-ca53.dtsi"
+#include "fsl-imx8-ca72.dtsi"
+#include <dt-bindings/clock/imx8qm-clock.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_hsio.h>
+#include <dt-bindings/soc/imx8_pd.h>
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "fsl,imx8qm";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ dpu1 = &dpu2;
+ ethernet1 = &fec2;
+ dsiphy1 = &mipi_dsi_phy2;
+ mipidsi1 = &mipi_dsi2;
+ ldb1 = &ldb2;
+ serial2 = &lpuart2;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &gpio5;
+ gpio6 = &gpio6;
+ gpio7 = &gpio7;
+ mmc0 = &usdhc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c8 = &i2c1_lvds1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0xc0000000 0 0x40000000>;
+ /* DRAM space - 1, size : 1 GB DRAM */
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * reserved-memory layout
+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
+ * Shouldn't be used at A core and Linux side.
+ *
+ */
+
+ decoder_boot: decoder_boot@0x84000000 {
+ no-map;
+ reg = <0 0x84000000 0 0x2000000>;
+ };
+ encoder_boot: encoder_boot@0x86000000 {
+ no-map;
+ reg = <0 0x86000000 0 0x400000>;
+ };
+ rpmsg_reserved: rpmsg@0x90000000 {
+ no-map;
+ reg = <0 0x90000000 0 0x400000>;
+ };
+ rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0 0x90400000 0 0x1C00000>;
+ };
+ decoder_rpc: decoder_rpc@0x92000000 {
+ no-map;
+ reg = <0 0x92000000 0 0x200000>;
+ };
+ encoder_rpc: encoder_rpc@0x92200000 {
+ no-map;
+ reg = <0 0x92200000 0 0x200000>;
+ };
+ dsp_reserved: dsp@0x92400000 {
+ no-map;
+ reg = <0 0x92400000 0 0x2000000>;
+ };
+ encoder_reserved: encoder_reserved@0x94400000 {
+ no-map;
+ reg = <0 0x94400000 0 0x800000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x3c000000>;
+ alloc-ranges = <0 0xd6000000 0 0x3c000000>;
+ linux,cma-default;
+ };
+
+ };
+
+ gic: interrupt-controller@51a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+ <0x0 0x51b00000 0 0xC0000>, /* GICR */
+ <0x0 0x52000000 0 0x2000>, /* GICC */
+ <0x0 0x52010000 0 0x1000>, /* GICH */
+ <0x0 0x52020000 0 0x20000>; /* GICV */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-parent = <&gic>;
+ };
+
+ mu8: mu@5d230000 {
+ compatible = "fsl,imx-m4-mu";
+ reg = <0x0 0x5d230000 0x0 0x10000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_lsio_mu8a>;
+ status = "disabled";
+ };
+
+ mu9: mu@5d240000 {
+ compatible = "fsl,imx-m4-mu";
+ reg = <0x0 0x5d240000 0x0 0x10000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_lsio_mu9a>;
+ status = "disabled";
+ };
+
+ mu: mu@5d1d0000 {
+ compatible = "fsl,imx8-mu";
+ reg = <0x0 0x5d1d0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ #mbox-cells = <4>;
+ status = "okay";
+
+ clk: clk {
+ compatible = "fsl,imx8qm-clk";
+ #clock-cells = <1>;
+ };
+
+ iomuxc: iomuxc {
+ compatible = "fsl,imx8qm-iomuxc";
+ };
+ };
+
+ mu13: mu13@5d280000 {
+ compatible = "fsl,imx8-mu-dsp";
+ reg = <0x0 0x5d280000 0x0 0x10000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,dsp_ap_mu_id = <13>;
+ status = "disabled";
+ };
+
+ mu_m0: mu_m0@2d000000 {
+ compatible = "fsl,imx8-mu0-vpu-m0";
+ reg = <0x0 0x2d000000 0x0 0x20000>;
+ interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <16>;
+ status = "okay";
+ };
+
+ mu1_m0: mu1_m0@2d020000 {
+ compatible = "fsl,imx8-mu1-vpu-m0";
+ reg = <0x0 0x2d020000 0x0 0x20000>;
+ interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <17>;
+ status = "okay";
+ };
+
+ mu2_m0: mu2_m0@2d040000 {
+ compatible = "fsl,imx8-mu2-vpu-m0";
+ reg = <0x0 0x2d040000 0x0 0x20000>;
+ interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <18>;
+ status = "okay";
+ };
+
+ vpu_decoder: vpu_decoder@2c000000 {
+ compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
+ boot-region = <&decoder_boot>;
+ rpc-region = <&decoder_rpc>;
+ reg = <0x0 0x2c000000 0x0 0x1000000>;
+ reg-names = "vpu_regs";
+ reg-csr = <0x2d080000>;
+ status = "disabled";
+ };
+
+ vpu_encoder: vpu_encoder@2d000000 {
+ compatible = "nxp,imx8qm-b0-vpuenc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot-region = <&encoder_boot>;
+ rpc-region = <&encoder_rpc>;
+ reserved-region = <&encoder_reserved>;
+ reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/
+ <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/
+ reg-names = "vpu_regs";
+ reg-rpc-system = <0x40000000>;
+
+ resolution-max = <1920 1080>;
+ fps-max = <120>;
+ status = "disabled";
+
+ core0@1020000 {
+ compatible = "fsl,imx8-mu1-vpu-m0";
+ reg = <0x1020000 0x20000>;
+ reg-csr = <0x1090000 0x10000>;
+ interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <17>;
+ fw-buf-size = <0x200000>;
+ rpc-buf-size = <0x80000>;
+ print-buf-size = <0x80000>;
+ };
+ core1@1040000 {
+ compatible = "fsl,imx8-mu2-vpu-m0";
+ reg = <0x1040000 0x20000>;
+ reg-csr = <0x10a0000 0x10000>;
+ interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <18>;
+ fw-buf-size = <0x200000>;
+ rpc-buf-size = <0x80000>;
+ print-buf-size = <0x80000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+ clock-frequency = <8000000>;
+ interrupt-parent = <&gic>;
+ };
+
+ smmu: iommu@51400000 {
+ compatible = "arm,mmu-500";
+ interrupt-parent = <&gic>;
+ reg = <0 0x51400000 0 0x40000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ interrupts = <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
+ };
+
+ cci: cci@52090000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x52090000 0 0x1000>;
+ ranges = <0 0 0x52090000 0x10000>;
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1",
+ "arm,cci-400-pmu";
+ reg = <0x9000 0x4000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+ };
+
+ #include "fsl-imx8qm-device.dtsi"
+};
+
+&A53_0 {
+ operating-points = <
+ /* kHz uV */
+ /* voltage is maintained by SCFW, so no need here */
+ 1200000 0
+ 1104000 0
+ 900000 0
+ 600000 0
+ >;
+ clocks = <&clk IMX8QM_A53_DIV>;
+ clock-latency = <61036>;
+ #cooling-cells = <2>;
+ /delete-property/ cpu-idle-states;
+};
+
+&A72_0 {
+ operating-points = <
+ /* kHz uV */
+ /* voltage is maintained by SCFW, so no need here */
+ 1596000 0
+ 1296000 0
+ 1056000 0
+ 600000 0
+ >;
+ clocks = <&clk IMX8QM_A72_DIV>;
+ clock-latency = <61036>;
+ #cooling-cells = <2>;
+ /delete-property/ cpu-idle-states;
+};
+
+
+&A53_1 {
+ /delete-property/ cpu-idle-states;
+};
+
+&A53_2 {
+ /delete-property/ cpu-idle-states;
+};
+
+&A53_3 {
+ /delete-property/ cpu-idle-states;
+};
+
+&A72_1 {
+ /delete-property/ cpu-idle-states;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/ {
+
+ aliases {
+ usbhost1 = &usbh3;
+ usbgadget0 = &usbg1;
+ };
+
+ usbh3: usbh3 {
+ compatible = "Cadence,usb3-host";
+ dr_mode = "host";
+ cdns3,usb = <&usbotg3>;
+ status = "okay";
+ };
+
+ usbg1: usbg1 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usbotg1>;
+ status = "okay";
+ u-boot,dm-spl;
+ };
+};
+
+&{/imx8qm-pm} {
+
+ u-boot,dm-spl;
+};
+
+&mu {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&{/regulators} {
+ u-boot,dm-spl;
+};
+
+®_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qm-mek} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+&pd_dma {
+ u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+ u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&lpuart0 {
+ u-boot,dm-spl;
+};
+
+&usbmisc1 {
+ u-boot,dm-spl;
+};
+
+&usbphy1 {
+ u-boot,dm-spl;
+};
+
+&usbotg1 {
+ u-boot,dm-spl;
+};
+
+&usbotg3 {
+ phys = <&usbphynop1>;
+ u-boot,dm-spl;
+};
+
+&usbphynop1 {
+ compatible = "cdns,usb3-phy";
+ reg = <0x0 0x5B160000 0x0 0x40000>;
+ #phy-cells = <0>;
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+};
+
+&flexspi0 {
+ u-boot,dm-spl;
+};
+
+&flash0 {
+ u-boot,dm-spl;
+};
+
+&wu {
+ u-boot,dm-spl;
+};
--- /dev/null
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qm-cockpit-a53.dtsi"
+
+/ {
+ model = "Freescale i.MX8QM MEK";
+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+ stdout-path = &lpuart0;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_otg1_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "sw-3p3-sd1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ u-boot,off-on-delay-us = <12000>;
+ };
+
+ epdev_on: fixedregulator@100 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_wlreg_on>;
+ pinctrl-1 = <&pinctrl_wlreg_on_sleep>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "epdev_on";
+ gpio = <&gpio1 13 0>;
+ enable-active-high;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx8qm-mek {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x06000021
+ SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x06000021
+ SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x06000021
+ SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x06000021
+ SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x06000021
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
+ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
+ SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
+ SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
+ SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061
+ SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
+ SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
+ SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061
+ SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061
+ SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061
+ SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
+ SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
+ SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
+ SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061
+ SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061
+ >;
+ };
+
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
+ SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
+ SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
+ SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
+ SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
+ SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
+ SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
+ SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
+ SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
+ SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
+ SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
+ SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
+ SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
+ SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
+ SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
+ SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
+ >;
+ };
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ SC_P_UART0_RX_DMA_UART0_RX 0x06000020
+ SC_P_UART0_TX_DMA_UART0_TX 0x06000020
+ >;
+ };
+
+ pinctrl_i2c0: i2c0grp {
+ fsl,pins = <
+ SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021
+ SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021
+ >;
+ };
+
+ pinctrl_pciea: pcieagrp{
+ fsl,pins = <
+ SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021
+ SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021
+ SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021
+ SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021
+ >;
+ };
+
+ pinctrl_typec: typecgrp {
+ fsl,pins = <
+ SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60
+ SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60
+ SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
+ SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
+ SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
+ >;
+ };
+ pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+ fsl,pins = <
+ SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c
+ SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c
+ >;
+ };
+
+ pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+ fsl,pins = <
+ SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c
+ SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c
+ >;
+ };
+
+ pinctrl_wlreg_on: wlregongrp{
+ fsl,pins = <
+ SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000
+ >;
+ };
+
+ pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
+ fsl,pins = <
+ SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000
+ >;
+ };
+ };
+};
+
+&gpio0 {
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&gpio6 {
+};
+
+&gpio7 {
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg3 {
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ /delete-property/ iommus;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-txid";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ fsl,rgmii_rxc_dly;
+ /delete-property/ iommus;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ at803x,eee-disabled;
+ at803x,vddio-1p8v;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ at803x,eee-disabled;
+ at803x,vddio-1p8v;
+ };
+ };
+};
+
+&flexspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash0: mt35xu512aba@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <29000000>;
+ spi-nor,ddr-quad-read-dummy = <8>;
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ status = "okay";
+
+ max7322: gpio@68 {
+ compatible = "maxim,max7322";
+ reg = <0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ typec_ptn5110: typec@50 {
+ compatible = "usb,tcpci";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ reg = <0x51>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ src-pdos = <0x380190c8 0x3803c0c8>;
+ port-type = "drp";
+ sink-disable;
+ default-role = "source";
+ status = "okay";
+ };
+};
+
+&lpuart0 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
+
+&i2c1_lvds0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ lvds-to-hdmi-bridge@4c {
+ compatible = "ite,it6263";
+ reg = <0x4c>;
+ };
+};
+
+&i2c1_lvds1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ lvds-to-hdmi-bridge@4c {
+ compatible = "ite,it6263";
+ reg = <0x4c>;
+ };
+};
+
+&pciea{
+ ext_osc = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pciea>;
+ disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+ epdev_on = <&epdev_on>;
+ status = "okay";
+};
+
+&sata {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pciea>;
+ clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+ /delete-property/ iommus;
+ status = "okay";
+};
+
+&tsens {
+ tsens-num = <6>;
+};
+
+&thermal_zones {
+ pmic-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens 5>;
+ trips {
+ pmic_alert0: trip0 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ pmic_crit0: trip1 {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&pmic_alert0>;
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&pmic_alert0>;
+ cooling-device =
+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&display {
+ ports = <&dpu1_disp0>, <&dpu1_disp1>;
+};
+
+/delete-node/ &dpu2;
+/delete-node/ &fec2;
+/delete-node/ &ldb2;
+/delete-node/ &isi_0;
+/delete-node/ &lpuart2;
+/delete-node/ &i2c1;
+/delete-node/ &usdhc1;
+/delete-node/ &i2c0;
+/delete-node/ &i2c1_lvds1;
+/delete-node/ &dpu2_intsteer;
+/delete-node/ &lvds_region2;
+/delete-node/ &ldb2_phy;
+/delete-node/ &irqsteer_lvds1;
+/delete-node/ &mipi_dsi2;
+/delete-node/ &mipi_dsi_bridge2;
+/delete-node/ &pinctrl_lvds1_lpi2c1;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/ {
+
+ aliases {
+ usbhost1 = &usbh3;
+ usbgadget0 = &usbg1;
+ };
+
+ usbh3: usbh3 {
+ compatible = "Cadence,usb3-host";
+ dr_mode = "host";
+ cdns3,usb = <&usbotg3>;
+ status = "okay";
+ };
+
+ usbg1: usbg1 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usbotg1>;
+ status = "okay";
+ u-boot,dm-spl;
+ };
+};
+
+&{/imx8qm-pm} {
+
+ u-boot,dm-spl;
+};
+
+&mu {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&{/regulators} {
+ u-boot,dm-spl;
+};
+
+&{/mu@5d1d0000/iomuxc/imx8qm-mek} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_lpuart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+ u-boot,dm-spl;
+};
+
+&pd_lsio {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+&pd_dma {
+ u-boot,dm-spl;
+};
+
+&pd_dma_lpuart2 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+ u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&lpuart2 {
+ u-boot,dm-spl;
+};
+
+&usbmisc1 {
+ u-boot,dm-spl;
+};
+
+&usbphy1 {
+ u-boot,dm-spl;
+};
+
+&usbotg1 {
+ u-boot,dm-spl;
+};
+
+&usbotg3 {
+ u-boot,dm-spl;
+};
+
+&usbphynop1 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&wu {
+ u-boot,dm-spl;
+};
--- /dev/null
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qm-cockpit-a72.dtsi"
+
+/ {
+ model = "Freescale i.MX8QM MEK";
+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+ aliases {
+ gpio8 = &max7322;
+ };
+
+ chosen {
+ bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
+ stdout-path = &lpuart2;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_otg1_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ epdev_on: fixedregulator@100 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_wlreg_on>;
+ pinctrl-1 = <&pinctrl_wlreg_on_sleep>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "epdev_on";
+ gpio = <&gpio1 13 0>;
+ enable-active-high;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ imx8qm-mek {
+ pinctrl_fec2: fec2grp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
+ SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
+ SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
+ SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
+ SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
+ SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
+ SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
+ SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
+ SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
+ SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
+ SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
+ SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
+ SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
+ >;
+ };
+
+ pinctrl_lpuart2: lpuart2grp {
+ fsl,pins = <
+ SC_P_UART0_RTS_B_DMA_UART2_RX 0x06000020
+ SC_P_UART0_CTS_B_DMA_UART2_TX 0x06000020
+ >;
+ };
+
+ pinctrl_i2c0: i2c0grp {
+ fsl,pins = <
+ SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021
+ SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021
+ >;
+ };
+
+ pinctrl_pciea: pcieagrp{
+ fsl,pins = <
+ SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021
+ SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021
+ SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021
+ SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021
+ >;
+ };
+
+ pinctrl_typec: typecgrp {
+ fsl,pins = <
+ SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60
+ SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60
+ SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
+ >;
+ };
+
+ pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+ fsl,pins = <
+ SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c
+ SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c
+ >;
+ };
+
+ pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+ fsl,pins = <
+ SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c
+ SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c
+ >;
+ };
+
+ pinctrl_wlreg_on: wlregongrp{
+ fsl,pins = <
+ SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000
+ >;
+ };
+
+ pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
+ fsl,pins = <
+ SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000
+ >;
+ };
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+};
+
+&gpio2 {
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+};
+
+&gpio5 {
+};
+
+&gpio6 {
+ status = "okay";
+};
+
+&gpio7 {
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ disable-over-current;
+ status = "disabled";
+};
+
+&usbotg3 {
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ /delete-property/ iommus;
+ status = "okay";
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ status = "okay";
+
+ max7322: gpio@68 {
+ compatible = "maxim,max7322";
+ reg = <0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ typec_ptn5110: typec@50 {
+ compatible = "usb,tcpci";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ reg = <0x51>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ src-pdos = <0x380190c8 0x3803c0c8>;
+ port-type = "drp";
+ sink-disable;
+ default-role = "source";
+ status = "okay";
+ };
+};
+
+&lpuart2 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart2>;
+ status = "okay";
+};
+
+&i2c1_lvds0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ lvds-to-hdmi-bridge@4c {
+ compatible = "ite,it6263";
+ reg = <0x4c>;
+ };
+};
+
+&i2c1_lvds1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ lvds-to-hdmi-bridge@4c {
+ compatible = "ite,it6263";
+ reg = <0x4c>;
+ };
+};
+
+&pciea{
+ ext_osc = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pciea>;
+ disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+ epdev_on = <&epdev_on>;
+ status = "okay";
+};
+
+&sata {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pciea>;
+ clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+ /delete-property/ iommus;
+ status = "okay";
+};
+
+&tsens {
+ tsens-num = <6>;
+};
+
+&thermal_zones {
+ pmic-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens 5>;
+ trips {
+ pmic_alert0: trip0 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ pmic_crit0: trip1 {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&pmic_alert0>;
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&pmic_alert0>;
+ cooling-device =
+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&display {
+ ports = <&dpu2_disp0>, <&dpu2_disp1>;
+};
+
+
+/delete-node/ &dpu1;
+/delete-node/ &fec1;
+/delete-node/ &ldb1;
+/delete-node/ &isi_0;
+/delete-node/ &lpuart0;
+/delete-node/ &lpuart1;
+/delete-node/ &lpuart3;
+/delete-node/ &lpuart4;
+/delete-node/ &i2c2;
+/delete-node/ &i2c3;
+/delete-node/ &i2c4;
+/delete-node/ &i2c1_lvds0;
+/delete-node/ &usdhc2;
+/delete-node/ &usdhc3;
+/delete-node/ &flexspi0;
+/delete-node/ &dpu1_intsteer;
+/delete-node/ &lvds_region1;
+/delete-node/ &ldb1_phy;
+/delete-node/ &hdmi;
+/delete-node/ &i2c0_hdmi;
+/delete-node/ &irqsteer_lvds0;
+/delete-node/ &mipi_dsi1;
+/delete-node/ &mipi_dsi_bridge1;
+/delete-node/ &i2c0_mipi_dsi0;
+/delete-node/ &lpspi0;
+/delete-node/ &mlb;
+/delete-node/ &pciea;
+/delete-node/ &pcieb;
+/delete-node/ &pinctrl_lvds0_lpi2c1;
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TARGET_IMX8QM_MEK_A53_ONLY=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_SPL=y
+CONFIG_PANIC_HANG=y
+CONFIG_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-cockpit-a53"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0xC0020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_MU_BASE_SPL=0x5d1e0000
+CONFIG_TARGET_IMX8QM_MEK_A72_ONLY=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_PANIC_HANG=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg,ANDROID_SUPPORT"
+CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-cockpit-a72"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_SMC_FUSE=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SC_THERMAL=y
+
+CONFIG_VIDEO=n
+CONFIG_VIDEO_IMX_HDP_LOAD=n
+
+CONFIG_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0xC0400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xD8000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0xC8000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_LIBAVB=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0xC0020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_MU_BASE_SPL=0x5d1e0000
+CONFIG_TARGET_IMX8QM_MEK_A72_ONLY=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_SPL=y
+CONFIG_PANIC_HANG=y
+CONFIG_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-cockpit-a72"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_SMC_FUSE=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=n
+CONFIG_USB_XHCI_IMX8=n
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_TCPC=n
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_CDNS3=n
+CONFIG_USB_CDNS3_GADGET=n
+CONFIG_USB_GADGET_DUALSPEED=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0xC0400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC2800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0xC8000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
projects / u-boot.git / commitdiff