arm64: dts: add flexspi in iMX8MN EVK dts

add flexspi support in iMX8MN EVK dts

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index ea7a765..150aa67 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -142,6 +142,22 @@
        };
 };
 
+&flexspi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi0>;
+       status = "okay";
+
+       flash0: mt25qu256aba@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "jedec,spi-nor";
+               spi-max-frequency = <80000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+       };
+};
+
 &i2c1 {
        clock-frequency = <400000>;
        pinctrl-names = "default";
@@ -514,6 +530,17 @@
                >;
        };
 
+       pinctrl_flexspi0: flexspi0grp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c4
+                       MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x84
+                       MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x84
+                       MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x84
+                       MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x84
+                       MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x84
+               >;
+       };
+
        pinctrl_gpio_led: gpioledgrp {
                fsl,pins = <
                        MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 86666bf..bdc31be 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1100,6 +1100,21 @@
                                status = "disabled";
                        };
 
+                       flexspi: spi@30bb0000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "nxp,imx8mm-flexspi";
+                               reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+                               reg-names = "fspi_base", "fspi-mmap";
+                               interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MN_CLK_QSPI_ROOT>;
+                               clock-names = "fspi";
+                               assigned-clock-rates = <80000000>;
+                               assigned-clocks = <&clk IMX8MN_CLK_QSPI>;
+                               assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
+                               status = "disabled";
+                       };
+
                        sdma1: dma-controller@30bd0000 {
                                compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
                                reg = <0x30bd0000 0x10000>;