MLK-25382: arm64: dts: fix the wrong pinctrl pad settings for lpspi
authorHan Xu <han.xu@nxp.com>
Thu, 6 May 2021 02:37:27 +0000 (21:37 -0500)
committerHan Xu <han.xu@nxp.com>
Thu, 6 May 2021 02:53:21 +0000 (21:53 -0500)
Correct the pad settings, the bit 2,3 should be reserved.

Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts
arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts
arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts
arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts

index cec2548..28d7afc 100644 (file)
 
                pinctrl_lpspi3: lpspi3grp {
                        fsl,pins = <
-                               IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK          0x600004c
-                               IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO          0x600004c
-                               IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI          0x600004c
-                               IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1          0x600004c
+                               IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK          0x6000040
+                               IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO          0x6000040
+                               IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI          0x6000040
+                               IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1          0x6000040
                        >;
                };
 
index d5689b1..a859253 100644 (file)
@@ -9,10 +9,10 @@
 
 &pinctrl_lpspi3 {
        fsl,pins = <
-               IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK          0x600004c
-               IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO          0x600004c
-               IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI          0x600004c
-               IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1          0x600004c
+               IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK          0x6000040
+               IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO          0x6000040
+               IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI          0x6000040
+               IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1          0x6000040
        >;
 };
 
index e06bbe6..819213e 100644 (file)
 
                pinctrl_lpspi3: lpspi3grp {
                        fsl,pins = <
-                               IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK          0x600004c
-                               IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO          0x600004c
-                               IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI          0x600004c
-                               IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1          0x600004c
+                               IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK          0x6000040
+                               IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO          0x6000040
+                               IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI          0x6000040
+                               IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1          0x6000040
                        >;
                };
 
index 302cc25..9df779e 100644 (file)
@@ -9,10 +9,10 @@
 
 &pinctrl_lpspi3 {
        fsl,pins = <
-               IMX8QM_SPI3_SCK_DMA_SPI3_SCK            0x600004c
-               IMX8QM_SPI3_SDO_DMA_SPI3_SDO            0x600004c
-               IMX8QM_SPI3_SDI_DMA_SPI3_SDI            0x600004c
-               IMX8QM_SPI3_CS0_DMA_SPI3_CS0            0x600004c
+               IMX8QM_SPI3_SCK_DMA_SPI3_SCK            0x6000040
+               IMX8QM_SPI3_SDO_DMA_SPI3_SDO            0x6000040
+               IMX8QM_SPI3_SDI_DMA_SPI3_SDI            0x6000040
+               IMX8QM_SPI3_CS0_DMA_SPI3_CS0            0x6000040
        >;
 };
 
index da0682d..187040b 100644 (file)
@@ -8,9 +8,9 @@
 &iomuxc {
        pinctrl_lpspi0: lpspi0grp {
                fsl,pins = <
-                       IMX8QM_SPI0_SCK_DMA_SPI0_SCK            0x600004c
-                       IMX8QM_SPI0_SDO_DMA_SPI0_SDO            0x600004c
-                       IMX8QM_SPI0_SDI_DMA_SPI0_SDI            0x600004c
+                       IMX8QM_SPI0_SCK_DMA_SPI0_SCK            0x6000040
+                       IMX8QM_SPI0_SDO_DMA_SPI0_SDO            0x6000040
+                       IMX8QM_SPI0_SDI_DMA_SPI0_SDI            0x6000040
                >;
        };
 
 
        pinctrl_lpspi3: lpspi3grp {
                fsl,pins = <
-                       IMX8QM_SPI3_SCK_DMA_SPI3_SCK            0x600004c
-                       IMX8QM_SPI3_SDO_DMA_SPI3_SDO            0x600004c
-                       IMX8QM_SPI3_SDI_DMA_SPI3_SDI            0x600004c
-                       IMX8QM_SPI3_CS0_DMA_SPI3_CS0            0x600004c
+                       IMX8QM_SPI3_SCK_DMA_SPI3_SCK            0x6000040
+                       IMX8QM_SPI3_SDO_DMA_SPI3_SDO            0x6000040
+                       IMX8QM_SPI3_SDI_DMA_SPI3_SDI            0x6000040
+                       IMX8QM_SPI3_CS0_DMA_SPI3_CS0            0x6000040
                >;
        };
 };
index a3b0141..2b49c8c 100755 (executable)
 
        pinctrl_lpspi2: lpspi2grp {
                fsl,pins = <
-                       IMX8QM_SPI2_SCK_DMA_SPI2_SCK            0x0600004c
-                       IMX8QM_SPI2_SDO_DMA_SPI2_SDO            0x0600004c
-                       IMX8QM_SPI2_SDI_DMA_SPI2_SDI            0x0600004c
+                       IMX8QM_SPI2_SCK_DMA_SPI2_SCK            0x06000040
+                       IMX8QM_SPI2_SDO_DMA_SPI2_SDO            0x06000040
+                       IMX8QM_SPI2_SDI_DMA_SPI2_SDI            0x06000040
                >;
        };
 
index ef997e2..7bbd5b6 100644 (file)
@@ -9,10 +9,10 @@
 
 &pinctrl_lpspi2 {
        fsl,pins = <
-               IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK          0x600004c
-               IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO          0x600004c
-               IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI          0x600004c
-               IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0          0x600004c
+               IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK          0x6000040
+               IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO          0x6000040
+               IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI          0x6000040
+               IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0          0x6000040
        >;
 };
 
index bc45356..c7bfeae 100644 (file)
@@ -8,9 +8,9 @@
 &iomuxc {
        pinctrl_lpspi0: lpspi0grp {
                fsl,pins = <
-                       IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK          0x600004c
-                       IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO          0x600004c
-                       IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI          0x600004c
+                       IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK          0x6000040
+                       IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO          0x6000040
+                       IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI          0x6000040
                >;
        };
 
 
        pinctrl_lpspi2: lpspi2grp {
                fsl,pins = <
-                       IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK          0x600004c
-                       IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO          0x600004c
-                       IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI          0x600004c
-                       IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0          0x600004c
+                       IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK          0x6000040
+                       IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO          0x6000040
+                       IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI          0x6000040
+                       IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0          0x6000040
                >;
        };
 };