Correct the pad settings, the bit 2,3 should be reserved.
Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
- IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c
- IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x600004c
- IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x600004c
- IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x600004c
+ IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
+ IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
+ IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
+ IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
>;
};
&pinctrl_lpspi3 {
fsl,pins = <
- IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c
- IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x600004c
- IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x600004c
- IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x600004c
+ IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
+ IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
+ IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
+ IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
- IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c
- IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x600004c
- IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x600004c
- IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x600004c
+ IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
+ IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
+ IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
+ IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
>;
};
&pinctrl_lpspi3 {
fsl,pins = <
- IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x600004c
- IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x600004c
- IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x600004c
- IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x600004c
+ IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x6000040
+ IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x6000040
+ IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x6000040
+ IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x6000040
>;
};
&iomuxc {
pinctrl_lpspi0: lpspi0grp {
fsl,pins = <
- IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x600004c
- IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x600004c
- IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x600004c
+ IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x6000040
+ IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x6000040
+ IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x6000040
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
- IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x600004c
- IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x600004c
- IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x600004c
- IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x600004c
+ IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x6000040
+ IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x6000040
+ IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x6000040
+ IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x6000040
>;
};
};
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <
- IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c
- IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c
- IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c
+ IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040
+ IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040
+ IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040
>;
};
&pinctrl_lpspi2 {
fsl,pins = <
- IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x600004c
- IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x600004c
- IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x600004c
- IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x600004c
+ IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x6000040
+ IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x6000040
+ IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x6000040
+ IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x6000040
>;
};
&iomuxc {
pinctrl_lpspi0: lpspi0grp {
fsl,pins = <
- IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK 0x600004c
- IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO 0x600004c
- IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI 0x600004c
+ IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK 0x6000040
+ IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO 0x6000040
+ IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI 0x6000040
>;
};
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <
- IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x600004c
- IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x600004c
- IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x600004c
- IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x600004c
+ IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x6000040
+ IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x6000040
+ IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x6000040
+ IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x6000040
>;
};
};