MLK-12483-5 mx6ul: Enable module fuse check EVK board

Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for
module fuse check. And modify board level codes for SD, FEC and EIM.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 9232e9f7637afa3b71b43ab2d1361582ec5a080a)
(cherry picked from commit 687b586bf7d3b0d2f796c8ea768e4fb450079adb)
(cherry picked from commit f1cdd3b004b15d950b35f3ef625af23c2f106f5a)
(cherry picked from commit e5ac66df336a1ce45f315ada5d8f1a73e8f22632)
(cherry picked from commit f43662fa184193d165973f0c50708f818b120708)
(cherry picked from commit 5a635cad834def6d5a624311e6db2666c6617276)

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 465b2db..8495387 100644 (file)
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -491,6 +491,8 @@ config TARGET_MX6UL_9X9_EVK
        select DM
        select DM_THERMAL
        select SUPPORT_SPL
+       select IMX_MODULE_FUSE
+       select OF_SYSTEM_SETUP
        imply CMD_DM
 
 config TARGET_MX6UL_14X14_EVK
@@ -500,6 +502,8 @@ config TARGET_MX6UL_14X14_EVK
        select DM
        select DM_THERMAL
        select SUPPORT_SPL
+       select IMX_MODULE_FUSE
+       select OF_SYSTEM_SETUP
        imply CMD_DM
 
 config TARGET_MX6UL_ENGICAM

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 2e9b4c9..d21f3a0 100644 (file)
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -283,6 +283,7 @@ static int setup_fec(void)
 {
        struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
        int ret;
+
        /*
         * Use 50M anatop loopback REF_CLK1 for ENET1,
         * clear gpr1[13], set gpr1[17].
@@ -293,17 +294,20 @@ static int setup_fec(void)
         * Use 50M anatop loopback REF_CLK2 for ENET2,
         * clear gpr1[14], set gpr1[18].
         */
-       clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
-                       IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
-
+       if (!check_module_fused(MODULE_ENET2)) {
+               clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+                               IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+       }
 
        ret = enable_fec_anatop_clock(0, ENET_50MHZ);
        if (ret)
                return ret;
 
-       ret = enable_fec_anatop_clock(1, ENET_50MHZ);
-       if (ret)
-               return ret;
+       if (!check_module_fused(MODULE_ENET2)) {
+               ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+               if (ret)
+                       return ret;
+       }
 
        enable_enet_clk(1);