MLK-16132-6 imx8mq: evk enable driver model

Enable pinctrl/dm mmc/dm i2c/dm regulator and pmic.
Since we do not enable DM for SPL, so move non dm
code to spl file.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index a5f6471..dd3599b 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -82,7 +82,9 @@ enum clk_root_index {
        ENET_PHY_REF_CLK_ROOT           = 85,
        NAND_CLK_ROOT                   = 86,
        QSPI_CLK_ROOT                   = 87,
+       MXC_ESDHC_CLK                   = 88,
        USDHC1_CLK_ROOT                 = 88,
+       MXC_ESDHC2_CLK                  = 89,
        USDHC2_CLK_ROOT                 = 89,
        I2C1_CLK_ROOT                   = 90,
        MXC_I2C_CLK                     = 90,

diff --git a/board/freescale/imx8mq_evk/imx8m_evk.c b/board/freescale/imx8mq_evk/imx8m_evk.c
index a345d9e..af05738 100644 (file)
--- a/board/freescale/imx8mq_evk/imx8m_evk.c
+++ b/board/freescale/imx8mq_evk/imx8m_evk.c
@@ -29,13 +29,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define QSPI_PAD_CTRL  (PAD_CTL_DSE2 | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
-                        PAD_CTL_FSEL2)
-
 #define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 
-#define I2C_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
-
 #define ENET_PAD_CTRL          (PAD_CTL_DSE7 | PAD_CTL_FSEL3)
 #define ENET_PAD_CTRL_MII_MDIO (PAD_CTL_ODE | PAD_CTL_DSE3 | PAD_CTL_FSEL0)
 #define ENET_PAD_CTRL_MII_MDC  (PAD_CTL_DSE3 | PAD_CTL_FSEL0)
@@ -102,177 +97,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 }
 #endif
 
-#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
-#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
-#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-       int ret = 0;
-
-       switch (cfg->esdhc_base) {
-       case USDHC1_BASE_ADDR:
-               ret = 1;
-               break;
-       case USDHC2_BASE_ADDR:
-               ret = !gpio_get_value(USDHC2_CD_GPIO);
-               return ret;
-       }
-
-       return 1;
-}
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-       IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-       IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
-       IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
-       IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
-       IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
-       IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
-       IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
-       IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
-       {USDHC1_BASE_ADDR, 0, 8},
-       {USDHC2_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_init(bd_t *bis)
-{
-       int i, ret;
-       /*
-        * According to the board_mmc_init() the following map is done:
-        * (U-Boot device node)    (Physical Port)
-        * mmc0                    USDHC1
-        * mmc1                    USDHC2
-        */
-       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-               switch (i) {
-               case 0:
-                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
-                       imx_iomux_v3_setup_multiple_pads(
-                               usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-                       gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
-                       gpio_direction_output(USDHC1_PWR_GPIO, 0);
-                       udelay(500);
-                       gpio_direction_output(USDHC1_PWR_GPIO, 1);
-                       break;
-               case 1:
-                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
-                       imx_iomux_v3_setup_multiple_pads(
-                               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-                       gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
-                       gpio_direction_output(USDHC2_PWR_GPIO, 0);
-                       udelay(500);
-                       gpio_direction_output(USDHC2_PWR_GPIO, 1);
-                       break;
-               default:
-                       printf("Warning: you configured more USDHC controllers"
-                               "(%d) than supported by the board\n", i + 1);
-                       return -EINVAL;
-               }
-
-               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-struct i2c_pads_info i2c_pad_info1 = {
-       .scl = {
-               .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
-               .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
-               .gp = IMX_GPIO_NR(5, 14),
-       },
-       .sda = {
-               .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
-               .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
-               .gp = IMX_GPIO_NR(5, 15),
-       },
-};
-
-static struct i2c_pads_info i2c_pad_info2 = {
-       .scl = {
-               .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | PC,
-               .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | PC,
-               .gp = IMX_GPIO_NR(5, 16),
-       },
-       .sda = {
-               .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | PC,
-               .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | PC,
-               .gp = IMX_GPIO_NR(5, 17),
-       },
-};
-
-static struct i2c_pads_info i2c_pad_info3 = {
-       .scl = {
-               .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | PC,
-               .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | PC,
-               .gp = IMX_GPIO_NR(5, 16),
-       },
-       .sda = {
-               .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | PC,
-               .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | PC,
-               .gp = IMX_GPIO_NR(5, 19),
-       },
-};
-#endif
-
-#ifdef CONFIG_POWER
-#define I2C_PMIC       0
-int power_init_board(void)
-{
-       struct pmic *p;
-       int ret;
-       unsigned int reg;
-
-       ret = power_pfuze100_init(I2C_PMIC);
-       if (ret)
-               return -ENODEV;
-
-       p = pmic_get("PFUZE100");
-       ret = pmic_probe(p);
-       if (ret)
-               return -ENODEV;
-
-       pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
-       printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
-
-       pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
-       if ((reg & 0x3f) != 0x18) {
-               reg &= ~0x3f;
-               reg |= 0x18;
-               pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
-       }
-
-       ret = pfuze_mode_init(p, APS_PFM);
-       if (ret < 0)
-               return ret;
-
-       return 0;
-}
-#endif
-
 #ifdef CONFIG_FEC_MXC
 #define FEC_RST_PAD IMX_GPIO_NR(1, 9)
 static iomux_v3_cfg_t const fec1_rst_pads[] = {
@@ -300,6 +124,7 @@ static void setup_iomux_fec(void)
 {
        imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, ARRAY_SIZE(fec1_rst_pads));
 
+       gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
        gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
        udelay(500);
        gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
@@ -346,13 +171,6 @@ int board_phy_config(struct phy_device *phydev)
 
 int board_init(void)
 {
-
-#ifdef CONFIG_SYS_I2C_MXC
-       setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-       setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-       setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-#endif
-
        board_qspi_init();
 
 #ifdef CONFIG_FEC_MXC

diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index a62f395..fd2c17d 100644 (file)
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -11,11 +11,16 @@
 #include <asm/io.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/arch/ddr_memory_map.h>
+#include <asm/arch/imx8mq_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
+#include <asm/arch/clock.h>
+#include <asm/imx-common/gpio.h>
 #include <asm/imx-common/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
 #include "ddr/lpddr4.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -26,7 +31,152 @@ void spl_dram_init(void)
        lpddr4_pub_train();
 }
 
-extern struct i2c_pads_info i2c_pad_info1;
+#define I2C_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+       .scl = {
+               .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+               .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+               .gp = IMX_GPIO_NR(5, 14),
+       },
+       .sda = {
+               .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+               .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+               .gp = IMX_GPIO_NR(5, 15),
+       },
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+       int ret = 0;
+
+       switch (cfg->esdhc_base) {
+       case USDHC1_BASE_ADDR:
+               ret = 1;
+               break;
+       case USDHC2_BASE_ADDR:
+               ret = !gpio_get_value(USDHC2_CD_GPIO);
+               return ret;
+       }
+
+       return 1;
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+                        PAD_CTL_FSEL2)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+       IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+       IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+       IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+       IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+       IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+       IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+       IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+       IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+       {USDHC1_BASE_ADDR, 0, 8},
+       {USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+       int i, ret;
+       /*
+        * According to the board_mmc_init() the following map is done:
+        * (U-Boot device node)    (Physical Port)
+        * mmc0                    USDHC1
+        * mmc1                    USDHC2
+        */
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               switch (i) {
+               case 0:
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+                       gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+                       gpio_direction_output(USDHC1_PWR_GPIO, 0);
+                       udelay(500);
+                       gpio_direction_output(USDHC1_PWR_GPIO, 1);
+                       break;
+               case 1:
+                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+                       gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+                       gpio_direction_output(USDHC2_PWR_GPIO, 0);
+                       udelay(500);
+                       gpio_direction_output(USDHC2_PWR_GPIO, 1);
+                       break;
+               default:
+                       printf("Warning: you configured more USDHC controllers"
+                               "(%d) than supported by the board\n", i + 1);
+                       return -EINVAL;
+               }
+
+               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC       0
+int power_init_board(void)
+{
+       struct pmic *p;
+       int ret;
+       unsigned int reg;
+
+       ret = power_pfuze100_init(I2C_PMIC);
+       if (ret)
+               return -ENODEV;
+
+       p = pmic_get("PFUZE100");
+       ret = pmic_probe(p);
+       if (ret)
+               return -ENODEV;
+
+       pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+       printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+       pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
+       if ((reg & 0x3f) != 0x18) {
+               reg &= ~0x3f;
+               reg |= 0x18;
+               pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
+       }
+
+       ret = pfuze_mode_init(p, APS_PFM);
+       if (ret < 0)
+               return ret;
+
+       return 0;
+}
+#endif
 
 void spl_board_init(void)
 {

diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 66501e2..8462a18 100644 (file)
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -9,3 +9,20 @@ CONFIG_OF_LIBFDT=y
 CONFIG_CMD_CACHE=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
 CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+# CONFIG_BLK is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y

diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index f66b1a6..fe8d775 100644 (file)
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -38,6 +38,20 @@
 #define CONFIG_SYS_DCACHE_OFF
 
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
 #endif
 
 #define CONFIG_REMAKE_ELF
@@ -239,21 +253,8 @@
 #define CONFIG_CMD_FUSE
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED             100000
 
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-
-/* USB3 */
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_HAS_FSL_XHCI_USB