MLK-17579 ARM64: dts: correct the pad setting for imx8 usdhc

according to IC suggestion, usdhc clock pad need to be configed as
input/output mode, for other usdhc pad, including the strobe pad, need
to be configed as normal mode.

This patch do the change on the imx8qxp and imx8qm board.

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
index ee942ad..5d3b894 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
@@ -396,7 +396,7 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000041
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
                                SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
                        >;
                };
@@ -413,7 +413,7 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000020
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000020
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000020
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000040
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000040
                                SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000020
                        >;
                };
@@ -430,7 +430,7 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000020
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000020
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000020
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000040
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000040
                                SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000020
                        >;
                };

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
index 54aae53..e2b0039 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
@@ -463,7 +463,7 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000041
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
                                SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
                        >;
                };
@@ -480,7 +480,7 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000020
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000020
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000020
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000040
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000040
                                SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000020
                        >;
                };
@@ -497,7 +497,7 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000020
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000020
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000020
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000040
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000040
                                SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000020
                        >;
                };

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
index 0c91b3a..6ac1c02 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
@@ -354,7 +354,7 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000041
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
                                SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
                        >;
                };
@@ -371,7 +371,7 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000020
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000020
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000020
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000040
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000040
                                SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000020
                        >;
                };
@@ -388,52 +388,52 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000020
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000020
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000020
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000040
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000040
                                SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000020
                        >;
                };
 
                pinctrl_usdhc2_gpio: usdhc2gpiogrp {
                        fsl,pins = <
-                               SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19     0x06000021
-                               SC_P_USDHC1_WP_LSIO_GPIO4_IO21          0x06000021
-                               SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22        0x06000021
+                               SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19     0x00000021
+                               SC_P_USDHC1_WP_LSIO_GPIO4_IO21          0x00000021
+                               SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22        0x00000021
                        >;
                };
 
                pinctrl_usdhc2: usdhc2grp {
                        fsl,pins = <
                                SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
-                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x06000021
-                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x06000021
-                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x06000021
-                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x06000021
-                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x06000021
-                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
+                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
+                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
+                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
+                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
+                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
+                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
                        >;
                };
 
                pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
                        fsl,pins = <
                                SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000040
-                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x06000020
-                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x06000020
-                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x06000020
-                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x06000020
-                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x06000020
-                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020
+                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000020
+                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000020
+                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000020
+                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000020
+                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000020
+                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
                        >;
                };
 
                pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
                        fsl,pins = <
                                SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000040
-                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x06000020
-                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x06000020
-                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x06000020
-                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x06000020
-                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x06000020
-                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020
+                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000020
+                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000020
+                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000020
+                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000020
+                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000020
+                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
                        >;
                };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
index 57b46ca..9b51a8f 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
@@ -414,7 +414,7 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000041
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
                        >;
                };
 
@@ -437,7 +437,7 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000020
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000020
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000020
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000040
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000040
                        >;
                };
 
@@ -453,51 +453,51 @@
                                SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000020
                                SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000020
                                SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000020
-                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000040
+                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000040
                        >;
                };
 
                pinctrl_usdhc2_gpio: usdhc2gpiogrp {
                        fsl,pins = <
-                               SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19     0x06000021
-                               SC_P_USDHC1_WP_LSIO_GPIO4_IO21          0x06000021
-                               SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22        0x06000021
+                               SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19     0x00000021
+                               SC_P_USDHC1_WP_LSIO_GPIO4_IO21          0x00000021
+                               SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22        0x00000021
                        >;
                };
 
                pinctrl_usdhc2: usdhc2grp {
                        fsl,pins = <
                                SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
-                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x06000021
-                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x06000021
-                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x06000021
-                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x06000021
-                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x06000021
-                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
+                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
+                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
+                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
+                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
+                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
+                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
                        >;
                };
 
                pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
                        fsl,pins = <
                                SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000040
-                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x06000020
-                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x06000020
-                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x06000020
-                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x06000020
-                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x06000020
-                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020
+                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000020
+                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000020
+                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000020
+                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000020
+                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000020
+                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
                        >;
                };
 
                pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
                        fsl,pins = <
                                SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000040
-                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x06000020
-                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x06000020
-                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x06000020
-                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x06000020
-                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x06000020
-                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020
+                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000020
+                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000020
+                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000020
+                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000020
+                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000020
+                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
                        >;
                };